EN25P05
Reserved bit. Status register bit locations 5 and 6 are reserved for future use. Current devices will
read 0 for these bit locations. It is recommended to mask out the reserved bit when testing the
Status Register. Doing this will ensure compatibility with future devices.
SRP bit. The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect
(WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow the
device to be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set
to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status
Register (SRP, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction
is no longer accepted for execution.
Write Status Register (WRSR) (01h)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded and executed, the device sets the
Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed
by the instruction code and the data byte on Serial Data Input (DI).
The instruction sequence is shown in Figure 8.. The Write Status Register (WRSR) instruction has
no effect on S6, S5, S1 and S0 of the Status Register. S6 and S5 are always read as 0. Chip Select
(CS#) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write
Status Register (WRSR) instruction is not executed. As soon as Chip Select (CS#) is driven High,
the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status
Register cycle is in progress, the Status Register may still be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register
cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is
reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block
Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in
Table 3.. The Write Status Register (WRSR) instruction also allows the user to set or reset the
Status Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status
Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware
Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the
Hardware Protected Mode (HPM) is entered.
Figure 8. Write Status Register Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
11
Rev. C, Issue Date: 2008/01/17
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
