EN25P05
Read Status Register (RDSR) (05h)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status
Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in
progress. When one of these cycles is in progress, it is recommended to check the Write In
Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the
Status Register continuously, as shown in Figure 7.
Figure 7. Read Status Register Instruction Sequence Diagram
Table 6. Status Register Bit Locations
S7
S6
0
S5
0
S4
0
S3
S2
S1
S0
SRP
BP1
BP0
WEL
WIP
Status Register Protect
Reserved Bits
Block Protect Bits
Write Enable Latch
Write In Progress
The status and control bits of the Status Register are as follows:
WIP bit. The WIP bit indicates whether the memory is busy with a Write Status Register, Program or
Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is
reset and no Write Status Register, Program or Erase instruction is accepted.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area
to be software protected against Program and Erase instructions. These bits are written with the
Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is
set to 1, the relevant memory area (as defined in Table 3.) becomes protected against Page
Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP1, BP0) bits can be written
provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is
executed if, and only if, both Block Protect (BP1, BP0) bits are 0.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
10
Rev. C, Issue Date: 2008/01/17
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
