EN25F20A
Table 4A. Instruction Set
Instruction Name
Byte 1
Code
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n-Bytes
EQPI
38h
(1)
RSTQIO
Release Quad I/O or
Fast Read Enhanced
Mode
FFh
RSTEN
66h
99h
06h
(2)
RST
Write Enable
Write Disable / Exit
OTP mode
Read Status
Register
Write Status
Register
04h
05h
(3)
(S7-S0)
S7-S0
(4)
continuous
01h
02h
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
D7-D0
Next byte continuous
(one byte
Page Program
Quad Input Page
Program
(5)
per 2 clocks,
continuous)
32h
(D7-D0, …)
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
Sector Erase
20h
52h
32KB Half Block
Erase (HBE)
64KB Block Erase
Chip Erase
D8h
C7h/ 60h
B9h
Deep Power-down
(6)
(7)
Release from Deep
Power-down, and
read Device ID
Release from Deep
Power-down
dummy
dummy
dummy
(ID7-ID0)
(M7-M0)
ABh
00h
01h
(ID7-ID0)
(M7-M0)
Manufacturer/
Device ID
dummy
dummy
90h
(ID7-ID0)
(M7-M0)
(ID15-ID8)
(ID7-ID0) (8)
Read Identification
Enter OTP mode
9Fh
3Ah
Read SFDP mode
and Unique ID
Number
(Next Byte)
continuous
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
5Ah
Notes:
1. Device accepts eight-clocks command in Standard SPI mode, or two-clocks command in Quad SPI mode
2. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
3. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from the
device on the DO pin
4. The Status Register contents will repeat continuously until CS# terminate the instruction
5. Quad Data
DQ0 = (D4, D0, …… )
DQ1 = (D5, D1, …… )
DQ2 = (D6, D2, …... )
DQ3 = (D7, D3, …... )
6. The Device ID will repeat continuously until CS# terminates the instruction
7. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminates the instruction.
00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID
8. (M7-M0) : Manufacturer, (ID15-ID8) : Memory Type, (ID7-ID0) : Memory Capacity
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Elite Semiconductor Memory Technology Inc.
11
Rev. C, Issue Date: 2016/07/22
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
