EN25F20A
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial
Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is
driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first,
on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).
The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by
both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has
been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed
(Fast_Read), Dual Output Fast Read (3Bh), Dual I/O Fast Read (BBh), Quad Input/Output
FAST_READ (EBh), Read Status Register (RDSR), Read Information Register (RDIFR) or Release
from Deep Power-down, and Read Device ID (RDI) instruction, the shifted-in instruction sequence is
followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out
sequence is being shifted out.
In the case of a Page Program (PP), Quad Input Page Program (QPP), Sector Erase (SE), Half Block
Erase (HBE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR), Write Enable
(WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (CS#) must be
driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That
is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#) being
driven Low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte,
nothing will happen and WEL will not be reset.
In the case of multi-byte commands of Page Program (PP), Quad Input Page Program (QPP) and
Release from Deep Power Down (RES ) minimum number of bytes specified has to be given,
without which, the command will be ignored.
In the case of Page Program, if the number of byte after the command is less than 4 (at least 1
data byte), it will be ignored too. In the case of SE, HBE and BE, exact 24-bit address is a must,
any less or more will cause the command to be ignored.
All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase
cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues
unaffected.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Elite Semiconductor Memory Technology Inc.
10
Rev. C, Issue Date: 2016/07/22
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
