PBM 990 80
Example:
A 32.768 kHz crystal oscillator design with max f
ACC2
= ±180 ppm will require a minimum low power mode stop time of (30-10)/
(250-180) = 0.29 s to fulfil the maximum real time error corresponding to the Bluetooth LPO clock requirement.
LPO oscillator characteristics
Conditions:
T
AMB
= -40 .. +85
o
C; V
DDCORE
= 2.3V .. 2.7V; Crystal capacitive load = 11 pF
Parameter
Oscillator start-up time from power-on
Symbol
t
START
Min
Typ
Max
3
Unit
s
Digital output pins characteristics
Conditions:
T
AMB
= -40 .. +85
o
C; C
LOAD
= 25 pF; V
DDCORE
= 2.3V .. 2.7V; V
DDIO1+2+4
= V
DDCORE
.. 3.3V; V
DDIo3
& V
DDFL
= 2.7 .. 3.3V
Rise and fall times are measured between 10% to 90% of the V
DDIO
level.
Type
All digital output and bidirectional output pins
Parameter
Rise time
Fall time
Symbol
t
R
t
F
Min
3.5
3.5
Max
20
15
Unit
ns
ns
USB transceiver pins, driver characteristics
The USB core and transceiver are certified according to the USB certification procedure performed by PMTC (Professional
Multimedia Test Centre).
Conditions:
T
AMB
= -40 .. +85
o
C; C
LOAD
= 50 pF; V
DDCORE
= 2.3V .. 2.7V; V
DDIO2
= 3.3V
Parameter
Driver Rise or Fall time
Driver differential Rise and Fall time matching (t
R
/ t
F
).
Output signal cross-over voltage
Driver output resistance (See Note)
Notes on USB Transceiver:
Symbol
t
R
, t
F
t
RFM
V
CRS
Z
DRV
Min
4
90
1.3
16
Typ
10
100
Max
20
110
2.0
28
Unit
ns
%
V
Ω
Excluding external resistor. In order to comply with USB specification, external resistors of 12
Ω
± 5% on each of the D+ and
D- branch are recommended. It is highly recommended to layout the PCB tracks for the USB D+ and D- lines side by side with
equal track length and resistance all the way to the USB connector.
PLL characteristics
To generate higher internal clock frequencies from the input clock XIN or CSXIN an internal PLL is included in PBM 990 80.
The PLL can be adapted to different input frequencies by programmable registers. Register values for the following crystal
frequencies have been verified: 12.00, 12.60, 12.80, 13.00, 14.40,16.80, 19.20,19.44, 24.00, 25.00, 30.00 and 32.00 MHz.
The PLL will output an internal 96 MHz clock which is divided down to a 48 MHz USB clock and a 32 MHz source clock to be
used for the rest of the system. This means that 32 MHz will be the maximum system (processor) clock frequency that can be
achieved when the PLL is used. The 32 MHz clock is divided down to the required internal clock frequency for each block.
The PLL is fed by an internal current reference block, IREF, which can be disabled by software when the PLL is not used in
order to save power. The start-up time of the PLL is dependent on whether the IREF is enabled prior to start of the PLL or not.
Conditions:
T
AMB
= -40 .. +85
o
C; V
DDCORE
& V
DDPLL
= 2.3V .. 2.7V; V
DDIO1
= V
DDCORE
.. 3.3V
Parameter
Input frequency
Start-up time, IREF enabled before start
Start-up time, IREF disabled before start
Symbol
f
IN
t
TST1
t
TST2
Min
12.00
Typ
13.00
Max
37.20
100
140
Unit
MHz
µs
µs
7
ERICSSON [ ERICSSON ]
