PBM 990 08/1MQ
SU_RXSOC (output)
Service Utopia interface
Receive start of cell. This signal points out the first
byte of the cell (when high).
This interface is a cell based Utopia interface, where
the Multi Service Chip is a slave. It can be configured
in both level 1 and level 2 mode.
SU_RXDATA[7:0] (output)
Receive data bus.
SU_TXCLK (input)
Transmit clock. The maximum frequency is 25
MHz.
QoS interface
SU_TXADDR[4:0] (input)
This is an interface to an external SRAM circuit. The
address range supports sizes up to 128 kbytes.
Transmit address. Only used in level 2 mode, and
is then used to select the Multi Service Chip in the
transmit direction.
QOS_WEZ (output)
Write enable. This signal writes data (when low)
into the external SRAM.
SU_TXCLAV (output)
Transmit cell available. This signal indicates
(when high) that the Multi Service Chip is ready to
receive a complete cell.
QOS_OE (output)
Output enable. This signal enables (when low) the
output on the external SRAM.
SU_TXENBZ (input)
Transmit data enable. This signal is set to low
during cell transfers, indicating that data is
available on the data bus.
QOS_ADDR[16:0] (output)
SRAM address bus.
QOS_DATA[7:0] (bidirectional)
SRAM data bus.
SU_TXSOC (input)
Transmit start of cell. This signal points out the
first byte of the cell (when high).
SU_TXDATA[7:0] (input)
Transmit data bus.
SU_RXCLK (input)
Receive clock. The maximum frequency is 25
MHz.
SU_RXADDR[4:0] (input)
Receive address. Only used in level 2 mode, and
is then used to select the Multi Service Chip in the
receive direction.
SU_RXCLAV (output)
Receive cell available. This signal indicates (when
high) that the Multi Service Chip is ready to
transmit a complete cell.
SU_RXENBZ (input)
Receive data enable. The Multi Service Chip puts
data on the data bus when signal goes low.
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