PBM 990 08/1MQ
AU_RXENBZ (output)
Telephony interface
Receive data enable. The Multi Service Chip
requests data from the PHY device by setting this
signal to low.
The telephony interface can work in two different
modes, PCM mode and E1/T1 mode, depending on
how the CE block is configured.
AU_RXSOC (input)
PCM_E1_T1_TXCLK (output)
Receive start of cell. This signal points out the first
byte of the cell (when high).
Transmit clock. The frequency is determined by
the network reference clock according to the
formulas below:
AU_RXDATA[7:0] (input)
Receive data bus.
PCM/E1: fPCM_E1_T1_TXCLK = (fNET_REF_CLK x 256)
T1:
fPCM_E1_T1_TXCLK = (fNET_REF_CLK x 193)
PCM_E1_T1_TXD (output)
Transmit data.
ATMF interfaces
ATMFx_TXD_X (analog)
Transmit data positive.
E1_T1_RXCLK (input)
Receive clock. This clock is only used in E1 and
T1 mode. The frequency must be 2.048 MHz for
E1 and 1.544 MHz for T1.
ATMFx_TXD_Y (analog)
Transmit data negative.
PCM_E1_T1_RXD (input)
Receive data.
ATMFx_RXD_X (analog)
Receive data positive.
PCM_FS (output)
ATMFx_RXD_Y (analog)
Receive data negative.
PCM frame sync. This signal determines the start
of the 125 µs frame, i.e. it points out the first
timeslot in the frame.
ATMFx_EQ_A (analog)
Equalizer filter.
PCM_MFS (output)
PCM multi frame sync. This signal determines the
start of the 2 ms multi frame, i.e. it points out the
first timeslot in each sixteenth frame.
ATMFx_EQ_B (analog)
Equalizer filter.
ATMFx_PLL_TST (analog)
PCM_DV[3:0] (output)
Test output from the internal PLL.
PCM channel data valid. These signals point out
the timeslot for each of the four CE channels.
10 (14)
ERICSSON [ ERICSSON ]
