PBL 403 05
VDD
VAPC
VSEL
VNEG
VDC
VDD
CA
C25
1µF
C26
1µF
C27
33nF
C11
470pF
L2
18nH
28
27
26
25
24
1
2
3
4
5
6
7
8
CA
VNEG
VDC
50Ω µstrip
C5
MS33
VSEL
VAPC
VD3_DCS2
VD3_DCS1
MS36
l = 1mm
w = 1.5mm
100pF
sma
C4
3.9pF
C15
470pF
l = 3.0mm
w = 0.3mm
VD1_DCS
RFIN_DCS
RFIN_GSM
C31
1µF
23
22
21
20
MS35
sma
sma
50Ω µstrip
50Ω µstrip
VD2_DCS
VD2_GSM
l = 3mm
w = 0.3mm
C28
10pF
C7
470pF
9
MS32
19
18
17
16
15
10
11
12
13
14
l = 7mm
C30
1µF
w = 0.3mm
C14
470pF
MS27
VD1_GSM
l = 4.0mm
w = 0.3mm
C23
8.2pF C1
7.5pF
RFOUT_GSM2
RFOUT_GSM1
L7
50Ω µstrip
C2
MS31
VD3_GSM1
VD3_GSM2
C3
l = 1.5mm
w = 1.5mm
4.7nH
100pF
sma
MS29
470pF
l = 6.0mm
w = 1.0mm
MS = Micro Strip (+measurements)
l = 3.0mm
w = 0.3mm
L9
120nH
C33
1µF
C32
1µF
The specifications apply to performance measured in test fixture.
VDD
Figure 6. Verification board schematic.
Figure 7. Verification board layout.
6
ERICSSON [ ERICSSON ]
