PBL 402 15
GndRF
EN
REF
VccPLL
GndPLL
GndCP
CP
VccCP
NC
NC
VccVCO
VTUNE
GndVCO
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
GndRF
VccRF
RXEN
TXEN
GATE
TX+
DIE
TX-
CK
ST
D
GndRF
RX+
RX-
GndRF
IFOUT+
IFOUT-
LD
VccIF
GndIF
IFIN+
IFIN-
PA Gate
13
14
15 16 17 18 19 20 21 22 23 24
GndFM
DTX
MOD
DRX
DSL
VccFM
RSSI
VccRSSI
CAP-
Figure 5. Pinning configuration.
Pin Descriptions:
Refer to pin configuration.
Pin number
Name
Function
Schematic in/output of the pin
V
CC
PLL
GndRSSI
SHOLD
CAP+
165 k
1
EN
Enable 3-wire interface and synthesiser.
EN
GndPLL
V
CC
PLL
2
REF
PLL reference clock input
REF
GndPLL
3
4
5
V
CC
PLL
GndPLL
GndCP
Voltage supply to the frequency synthesiser.
Ground connection to the frequency synthesiser.
Ground connection to the charge pump.
Clamp to GndPLL
A diode to GndCP and GndRF
A diode to GndPLL and GndVCO
V
CC
CP
6
CP
Charge pump output.
CP
GndCP
7
V
CC
CP
Voltage supply to the charge pump.
Clamp to GndCP
3
ERICSSON [ ERICSSON ]
