PBL 402 15
Word A Table.
Data address
Name
Default
Description
D0
CE
CL
0
0 = Chip disable
1 = Chip enable
Active low on the external EN pin will also enable the chip
0 = Internal control flags
D1
0
1 = External control lines
D2
D3
D4
D5
D6
D7
CNT_A0
CNT_A1
CNT_A2
CNT_A3
CNT_A4
CNT_M
0
0
0
0
0
0
Synthesiser frequency counter A bit 0 (LSB) to 4 (MSB)
Synthesiser frequency counter M
0 → M = 32 (used for receive)
1 → M = 34 (used for transmit)
Synthesiser reference counter R
0 → R = 6 used if REF = 10.368 MHz
1 → R = 8 used if REF = 13.824 MHz
D8
CNT_R
0
D9
(a)
0
0
Receiver VCO enable . 000 = VCO disabled.
Any other setting activates the VCO. (default 100)
D10
D11
D12
D13
D14
D15
D16
(a)
RXVCO_EN
(a)
0 (1)
0
0
0 (1)
0
0
Transmit VCO enable . 000 = VCO disabled.
Any other setting activates the VCO. (default 100)
(a)
TXVCO_EN
Reserved
DRX_T
(a)
1 = Analog signal output at DRX pin.
0 = Digital data output at DRX pin.
D17
D18
TX_P0
TX_P1
0
0
Transmit power trim bits
0 (LSB) to 1 (MSB)
00 = -1.3 dB Min.
01 = Nominal power
10 = +1.3 dB
11 = +1.9 dB Max.
D19
RX_G
0
IRRX gain.
0 = +0dB extra
1 = +9dB extra
D20
D21
D22
IFT0
IFT1
IFT2
1
1
0
Demodulation IF frequency trim bits 0 (LSB) to 2 (MSB).
This should be programmed to the default settings.
a. Use ´0´ only.
b. Recommended at all times.
11