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PBL386502SOT 参数 Datasheet PDF下载

PBL386502SOT图片预览
型号: PBL386502SOT
PDF下载: 下载PDF文件 查看货源
内容描述: 用户线接口电路 [Subscriber Line Interface Circuit]
分类和应用:
文件页数/大小: 16 页 / 143 K
品牌: ERICSSON [ ERICSSON ]
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PBL 386 50/2  
gized, dc current flows and the compara-  
tor input voltage reverses polarity.  
Figure 12 gives an example of a ring  
trip detection network. This network is  
applicable, when the ring voltage is  
superimposed on VB and is injected on  
the ring lead of the two-wire port. The dc  
voltage across sense resistor RRT is  
monitored by the ring trip comparator  
input DT and DR via the network R1, R2,  
R3, R4, C1 and C2. With the line on-hook  
(no dc current) DT is more positive than  
DR and the DET output will report logic  
level high, i.e. the detector is not tripped.  
When the line goes off-hook, while  
ringing, a dc current will flow through the  
loop including sense resistor RRT and will  
cause input DT to become more negative  
than input DR. This changes output DET  
to logic level low, i.e. tripped detector  
condition. The system controller (or line  
card processor) responds by de-energiz-  
ing the ring relay, i.e. ring trip.  
VTX  
PBL386 50/2  
CODEC  
DC-GND  
RT  
I
IRT  
IRSN  
IRRX  
RRX  
_
RSN  
+
IRR  
+1.25 V  
UREFcodec  
RR  
Figure 14. CODEC receive interface.  
and the programmed dc characteristic,  
with the longitudinal current compensa-  
tion (see section Longitudinal Imped-  
ance) not active, to the line on the  
RINGX pin.  
Ringing State  
The ring relay driver and the ring trip  
detector are activated and the ring trip  
detector is indicating off hook with a logic  
low level at the detector output.  
Complete filtering of the 20 Hz ac  
component at terminal DT and DR is not  
necessary. A toggling DET output can be  
examined by a software routine to  
determine the duty cycle. When the DET  
output is at logic level low for more than  
half the time, off-hook condition is  
The loop current detector is active.  
The SLIC is in the active normal state.  
Active Polarity Reversal State  
Active States  
TIPX and RINGX polarity is reversed  
from the Active State: RINGX is the  
terminal closest to ground and sources  
loop current while TIPX is the more  
negative terminal and sinks current. Vf  
signal transmission is normal. The loop  
current or the ground key detector is  
activated. The loop current detector is  
indicating off hook with a logic low level  
and the ground key detector is indicating  
active ground key with a logic high level  
present at the detector output.  
TIPX is the terminal closest to ground  
and sources loop current while RINGX is  
the more negative terminal and sinks  
loop current. Vf signal transmission is  
normal. The loop current or the ground  
key detector is activated. The loop  
current detector is indicating off hook  
with a logic low level and the ground key  
detector is indicating active ground key  
with a logic high level present at the  
detector output.  
In PBL 386 50/2 a line voltage meas-  
urement feature is available in the active  
state, which may be used for line length  
estimations or for line test purposes. The  
line voltage is presented on the detector  
output as a pulse at logic high level with  
a pulsewidth of 5.5 µs/V. To start the line  
voltage measurement this mode has to  
be entered from the Active State with the  
loop or ground key detector active. The  
pulse presented at the DET output  
proportional to the line voltage starts  
when entering the line voltage measuring  
mode.  
indicated.  
Relay driver  
The PBL 386 50/2 SLIC incorporates a  
ring relay driver designed as open  
collector (npn) with a current sinking  
capability of 50mA. The drive transistor  
emitter is connected to BGND. The relay  
driver has an internal zener diode clamp  
for inductive kickback voltages. Care  
must be taken when using the relay  
driver together with relays that have high  
impedance.  
Overvoltage Protection  
The PBL 386 50/2 SLIC must be  
protected against overvoltages on the  
telephone line caused by lightning, ac  
power contact and induction. Refer to  
Maximum Ratings, TIPX and RINGX  
terminals, for maximum allowable  
continuous and transient currents that  
may be applied to the SLIC.  
Control Inputs  
The PBL 386 50/2 SLIC have three  
digital control inputs, C1, C2 and C3.  
A decoder in the SLIC interprets the  
control input condition and sets up the  
commanded operating state.  
C1 to C3 are internal pull-up inputs.  
Open Circuit State  
Secondary Protection  
In the Open Circuit State the TIPX and  
RINGX line drive amplifiers as well as  
other circuit blocks are powered down.  
This causes the SLIC to present a high  
impedance to the line. Power dissipation  
is at a minimum and no detectors are  
active.  
The circuit shown in figure 12 utilizes  
series resistors together with a  
programmable overvoltage protector  
(e.g. PowerInnovations TISPPBL2),  
serving as a secondary protection.  
Tip Open State  
Tip Open State is used for ground start  
signalling.  
In this state the SLICs present a high  
impedance to the line on the TIPX pin  
15