PBL 386 15/1
Positive overvoltages are clamped to
ground by a diode. Negative overvoltages
are initially clamped close to the SLIC neg-
ative supply rail voltage and the protector
will crowbar into a low voltage on-state
condition, by firing an internal thyristor.
Agatedecouplingcapacitor,CGG,isneed-
ed to carry enough charge to supply a high
enoughcurrenttoquicklyturnonthethyris-
tor in the protector. CGG should be placed
close to the overvoltage protection device.
Without the capacitor even the low induc-
tance in the track to the VB supply will limit
the current and delay the activation of the
thyristor clamp.
The fuse resistors RF serve the dual
purposes of being non- destructive
energy dissipators, when transients are
clamped and of being fuses, when the
line is exposed to a power cross. If a
PTC is chosen for RF , note that it is
important to always use the PTC´s in
series with resistors not sensitive to
temperature, as the PTC will act as a
capacitance for fast transients and
Power-up Sequence
Overvoltage Protection
No special power-up sequence is neces-
sary except that ground has to be present
before all other power supply voltages.
The digital inputs C1 to C3 are internal
pull-up terminals.
PBL 386 15/1 must be protected against
overvoltages on the telephone line. The
overvoltages could be caused for instance
by lightning, ac power contact and induc-
tion. Refer to Maximum Ratings, TIPX and
RINGX terminals, for maximum continu-
ous and transient voltages.
Printed Circuit Board Layout
Care in Printed Circuit Board (PCB) layout
is essential for proper function;
Secondary Protection
The components connecting to the RSN
input should be placed in close proximity to
that pin, such that no interference is inject-
ed into the RSN pin. Ground plane sur-
rounding the RSN pin is advisable.
Analog ground (AGND) should be con-
nected to battery ground (BGND) on the
PCB in one point.
Thecircuitshowninfigure15utilizesseries
resistors together with a programmable
overvoltage protector (e g Power Innova-
tions TISP PBL2), serving as a secondary
protection.
The TISP PBL2 is a dual forward-con-
ducting buffered p-gate overvoltage pro-
tector. The protector gate references the
protection (clamping) voltage to negative
supplyvoltage(i.e. thebatteryvoltage, VB).
As the protection voltage will track the
negative supply voltage the overvoltage
stress on the SLIC is minimized.
RLC and RREF should be connected to
AGND with short leads. Pin LP and pin
PSG are sensitive to leakage currents.
RSG andCLP connectionstoVBAT2should
be short and very close to each other.
CB and CB2 must be connected with short
wide leads.
therefore will not protect the TISP.
Information given in this data sheet is believed to be
accurate and reliable. However no responsibility is
assumed for the consequences of its use nor for any
infringement of patents or other rights of third
parties which may result from its use. No license is
granted by implication or otherwise under any patent
or patent rights of Ericsson Microelectronics AB.
These products are sold only according to Ericsson
Microelectronics general conditions of sale, unless
otherwise confirmed in writing.
Ordering Information
Package
Temp. Range
Part No.
28pin SSOP Tape & Reel -40° - + 85 °C
PBL 386 15/1 SHT
Specifications subject to change without
notice.
1522-PBL 386 15/1 Uen Rev. R1A
© Ericsson Microelectronics AB, 2000
This product is an original Ericsson
product protected by US, European and
other patents.
Ericsson Microelectronics
SE-164 81 Kista-Stockholm, Sweden
Telephone: +46 8 757 50 00
18
ERICSSON [ ERICSSON ]
