PBL 386 15/1
PBL 386 15/1
KR
RTX
RRLY
VTX
AGND
RSN
DET
+12 V /+5V
RING
-
CGG
out
TS
RT
RB
+
CHP
RRX
RF1
HP
RINGX
BGND
out
CRC
CTC
OVP
DB2
C1
VB
CODEC/
Filter
RF2
TIP
TIPX
VBAT
VBAT2
NC
C2
C3
VCC
PLD
PLC
SPR
REF
VEE
NC
VCC
VB2
VB
RLD
CB2
CB
DBB
DB
RLC
PSG
LP
CSPR
RREF
SYSTEM CONTROL
INTERFACE
R1
CLP
DT
ERG
DR
VEE
RRF
RRT
NC
R2
C2
C1
R3
R4
VCC
VEE
+5 V
CVCC
CVEE
VBAT<VEE<-5 V
RESISTORS (values according to IEC-
63 E96 series):
CAPACITORS: (values according to
IEC-63 E6 series):
DIODES:
DB
DB2
DBB
= 1N4448
= 1N4448
= 1N4448
1
RLD
RLC
RREF
RT
RTX
RB
RRX
R1
R2
= 49.9 kΩ 1%
= 18.7 kΩ 1%
/
/
/
/
/
/
/
/
/
/
/
10 W
10 W
10 W
10 W
10 W
10 W
10 W
10 W
10 W
10 W
10 W
CB
= 100 nF 100 V 20%
= 150 nF 100 V 20%
1
1
1
1
1
1
1
1
1
1
CB2
CVCC
CVEE
CTC
CRC
CHP
CLP
CGG
C1
= 15 kΩ
1%
= 100 nF
= 100 nF
10 V 20%
10 V* 20%
OVP:
= 105 kΩ 1%
= 32.4 kΩ 1%
= 57.6 kΩ 1%
= 105 kΩ 1%
= 604 kΩ 1%
= 604 kΩ 1%
= 249 kΩ 1%
= 280 kΩ 1%
Secondary protection ( e g Power
Innovations TISP PBL2). The ground termin-
als of the secondary protection should be
connected to the common ground on the
Printed Board Assembly with a track as short
and wide as possible, preferably a
groundplane.
= 1.0 nF 100 V 20%
= 1.0 nF 100 V 20%
= 68 nF
100 V 20%
= 470 nF 100 V 20%
= 220 nF 100 V 20%
= 330 nF 63 V 10%
= 330 nF 63 V 10%
R3
R4
C2
RRT
RRF
RF1, RF2
= 332 Ω
= 332 Ω
= Line resistor, 40 Ω 1% match
5% 2 W
5% 2 W
CSPR
= optional
10 V 20%
*100V if VEE pin connected to VBAT, VBAT2
Figure 15. Single-channel subscriber line interface with PBL 386 15/1 and combination CODEC/filter
through the loop including sense resistor
Detector Output (DET)
Relay driver
RRT and will cause the input DT to become
more negative than input DR. This chang-
es the output on the DET pin to logic level
low, i.e. tripped detector condition. The
system controller (or line card processor)
responds by de-energizing the ring relay
via the SLIC, i.e. ring trip.
Completefilteringofthe20Hzaccompo-
nent at terminals DT and DR is not neces-
sary. A toggling DET output can be exam-
ined by a software routine to determine the
duty cycle. Off-hook condition is indicated
whentheDEToutputisatlogiclevellowfor
more than half the time.
The PBL 386 15/1 SLIC incorporates a
The PBL 386 15/1 SLIC incorporates a
detector output driver designed as open ringrelaydriverdesignedasopencollector
collector (npn) with a current sinking capa- (npn) with a current sinking capability of 50
bility of min 3 mA, and a 10 kΩ pull-up mA.The emitter of the drive transistor is
resistor. The emitter of the drive transistor connected to BGND. The relay driver has
is connected to AGND. A LED can be aninternalzenerdiodeclamptoprotectthe
connected in series with a resistor (≈1 kΩ) SLICfrominductivekick-backvoltages.No
at the DET output to visualize, for example external clamp is needed.
loop status.
15
ERICSSON [ ERICSSON ]
