PBL 386 11/2
Note that it is always important to use
resistors not sensitive to temperature in
series with PTC´s since the PTC acts as a
capacitance for transients. Otherwise the
SLIC is not protected properly.
Secondary Protection
Notes
Thecircuitshowninfigure13utilizesseries
resistors together with a programmable
overvoltage protector (e g Power Innova-
tions TISP PBL1 or PBL2), serving as a
secondary protection.
The TISP PBLx is a dual forward-con-
ducting buffered p-gate overvoltage pro-
tector. The protector gate references the
protection (clamping) voltage to negative
supplyvoltage(i.e. thebatteryvoltage, VB).
As the protection voltage will track the
negative supply voltage the overvoltage
stress on the SLIC is minimised.
Positive overvoltages are clamped to
ground by a diode. Negative overvoltages
are initially clamped close to the SLIC neg-
ative supply rail voltage and the protector
will crowbar into a low voltage on-state
condition, by firing an internal thyristor.
Agatedecouplingcapacitor,CGG,isneed-
ed to carry enough charge to supply a high
enoughcurrenttoquicklyturnonthethyris-
tor in the protector. CGG should be placed
close to the overvoltage protection device.
Without the capacitor even the low induc-
tance in the track to the VB supply will limit
the current and delay the activation of the
thyristor clamp.
Note 11.
2.5VPeak ifAOV-pinisleftopenand0.6VPeak
if AOV-pin is connected to AGND.
Power-up Sequence
Note 12.
No special power-up sequence is neces-
sary except that ground has to be present
before all other power supply voltages.
The digital inputs C1 to C3 are internal
pull-up terminals.
RFeed lower than 2x50Ω will reduce noise
and PSRR performance in resistive loop
region (reference D in figure 14). Better
PSRR performance can be achieved by
increasing CLP and CHP.
Printed Circuit Board Layout
Care in Printed Circuit Board (PCB) layout
is essential for proper function;
Note 13.
If the momentary value of the current in
TIPX-pin or RINGX-pin exceeds 85mA
harmonic distortion specification can be
derated.
The components connecting to the RSN
input should be placed in close proximity to
that pin, such that no interference is inject-
ed into the RSN pin. Ground plane sur-
rounding the RSN pin is advisable.
Analog ground (AGND) should be con-
nected to battery ground (BGND) on the
PCB in one point.
RLC and RREF should be connected to
AGND with short leads. Pin LP, pin PSG
and pin AOV are sensitive to leakage cur-
rents. Pin AOV should be surrounded by a
guardring connected to AGND.
Note 14.
The accurate equation for RLC is:
500 10.4 • In (ILProg • 32)
ILProg
RLC
=
-
ILProg
Note 15.
5.3V when AOV-pin is not connected, 3.9V
when AOV-pin is connected to AGND.
The programmed line current, ILProg, must
be less than 55 mA when using the TISP
PBL1 to ensure that the TISP holding cur-
rent is not exceeded. For higher pro-
grammed line currents, the TISP PBL2 is
recommended.
The fuse resistors RF serve the dual pur-
poses of being non- destructive energy
dissipators, when transients are clamped
and of being fuses, when the line is ex-
posed to a power cross.
RSG and CLP connections to VBAT should
be short and very close to each other.
CB and CB2 must be connected with short
wide leads.
Note 16.
1.6VRMS if AOV-pin is left open and 0.4VRMS
if AOV-pin is connected to AGND.
Note 17.
6.1VwhenAOV-pinisleftopen, 4.2Vwhen
AOV-pin is connected to AGND.
17
ERICSSON [ ERICSSON ]
