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PBL3852 参数 Datasheet PDF下载

PBL3852图片预览
型号: PBL3852
PDF下载: 下载PDF文件 查看货源
内容描述: 通用传输电路 [Universal Transmission Circuit]
分类和应用:
文件页数/大小: 24 页 / 407 K
品牌: ERICSSON [ ERICSSON ]
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PBL 3852  
Int. ref.0.855V  
30k  
To gain regulation  
Line  
R10  
C5  
Da  
7
Ref.  
(1.16V)  
RTC  
R14  
GR  
10  
Db  
DC 1  
R8  
2.2k  
+
R15  
C7  
Rectifier output  
In ref.=0.855V  
0V  
Signal at GR without C7  
Figure 18. The dynamic limiter function  
V
Amplitude limiter  
16  
14  
12  
10  
8
V
L
Amplitude limiter  
(1x diode  
I R +  
S
VTsat  
7
1x Vce)  
V
4V  
Tline  
p-p  
6
4
2
I
L
mA  
20  
40  
60  
80  
100  
120  
Figure 19. Transmitter output signal  
limiter. See fig. 22 for data.  
Power down and input PD  
dialling can be improved by switching the  
voltage at this input. Most of the modern  
processors used for LD-dialling do also  
supply a ”window” signal for the duration  
of the LD-digit stream. This signal can be  
used for the PD input. An improvement of  
receiver and transmitter output swing at  
very low line currents (IL<10mA) can be  
achieved by controlling this PD input with  
two resistors and a diode, maybe a  
capacitor C1 is necessary, see fig. 21.  
The circuit can be made to work down at  
1.8V line voltage and 2.8mA line current.  
Great care has to be taken to secure  
against a possible latchup.  
restricting the internal reference voltage  
buid up and the circuit to ”wake up”. (It is  
good practice to isolate the input with a  
diode according to fig. 21, an open  
collector drain can also be used). If the  
adjusting feature with the two resistors is  
used, it does not endanger the ”waking  
up” process because the line voltage via  
R19 will lift the level at PD input over the  
critical reference voltage level of 1.16V. In  
case this input is not used it should be left  
”open”.  
During pulse dialling or register recall  
(time controlled line break) the telephone  
line is interrupted, hence the transmis-  
sion and peripheral circuits are not  
supplied during the breaks from the  
line.The circuit has therefore an internal  
power-down function that automatically  
shuts down the current consuming parts  
when the line voltage drops under a  
certain level. This function reduces the  
internal current consumption I+C  
to120µA that in its turn minimizes the  
charge up time of the capacitor C9 when  
the line feed returns. The timing and pulse  
shape at LD - dialling is improved. In  
some cases the parameters around LD -  
The PD input should not be held ”down”  
at hook-on or at start to hook-off this  
13  
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