Ericsson Internal
E
SECSUND
PRODUCT SPECIFICATION
4 (7)
Prepared (also subject responsible if other)
No.
30/1301-BMR 451 0002 Uen
15
Technical Specification
Approved
Checked
Date
Rev
Reference
EN/LZT 146 401 R4A May 2015
BMR 451 Digital PoL Regulators
Input 4.5-14 V, Output up to 40 A / 132 W
2015-05-15
PJ1
© Ericsson AB
When starting by applying input voltage the control circuit boot-
up time adds an additional 10 ms delay. Please contact your
local Ericsson Power Modules representative for design
support of custom configurations or appropriate SW tools for
design and down-load of new configurations.
Output Voltage Sequencing
A group of regulators may be configured to power up in a
predetermined sequence. This feature is especially useful
when powering advanced processors, FPGAs, and ASICs that
require one supply to reach its operating voltage prior to
another supply reaching its operating voltage. Multi-regulator
sequencing can be achieved by configuring each device start
delay and rise time through the PMBus and use the same
remote control start signal. Please contact your local Ericsson
Power Modules representative for design support of custom
configurations or appropriate SW tools for design and down-
load of new configurations.
SMBus timing diagram
Voltage Margining Up/Down
The regulator can momentarily adjust its output higher or lower
than its nominal voltage setting in order to determine whether
the load device is capable of operating over its specified supply
voltage range. This provides a convenient method for
dynamically testing the operation of the load circuit over its
supply margin or range. It can also be used to verify the
function of supply voltage supervisors. Margin limits of the
nominal output voltage ±5% are default, but the margin limits
can be reconfigured using the PMBus interface to as high as
10% or as low as 0V. Please contact your local Ericsson Power
Modules representative for design support of custom
configurations or appropriate SW tools for design and down-
load of new configurations.
Pre-Bias Startup Capability
Pre-bias startup often occurs in complex digital systems when
current from another power source is fed back through a dual-
supply logic component, such as FPGAs or ASICs. The
BMR 451 product family incorporates synchronous rectifiers,
but will not sink current during startup, or turn off, or whenever
a fault shuts down the product in a pre-bias condition with right
configuration. Please contact your local Ericsson Power
Modules representative for design support of custom
configurations or appropriate SW tools for design and down-
load of new configurations.
I2C/SMBus Setup and Hold Times – Definitions
The setup time, tset, is the time the data, SDA, must be stable
before the rising edge of the clock signal, SCL. The hold time
t
hold, is the time the data must be stable after the rising edge of
the clock signal, SCL. If these times are violated incorrect data
can be captured or meta-stability can occur and the bus
communication fails.
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