Page 92
Epson Research and Development
Vancouver Design Center
Table 7-25: Single Color 8-Bit Panel A.C. Timing (Format 1)
Min.
Setting
28
Max.
Setting
1268 Ts (note 1)
Symbol
Parameter
Typical
Units
t1
t2
t3
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
note 2
12
11
Ts
Ts
FPLINE pulse width
t4
FPLINE period
40
5
7
3
5
note 3
note 4
note 4
note 5
note 5
20
1280
229
231
227
229
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
t5a
t5b
t6a
t6b
t7a
t7b
t8
t9a
t9b
t10a
t10b
t11a
t11b
t12
t13
t14
t15
FPSHIFT2 falling edge to FPLINE rising edge, 4 bpp or 8 bpp
FPSHIFT2 falling edge to FPLINE rising edge, 15/16 bpp
FPSHIFT falling edge to FPLINE rising edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE rising edge, 15/16 bpp
FPLINE falling edge to FPSHIFT2 rising, FPSHIFT falling edge, 4/8 bpp
FPLINE falling edge to FPSHIFT2 rising, FPSHIFT falling edge, 15/16 bpp
FPSHIFT2, FPSHIFT period
FPSHIFT falling edge to FPLINE falling edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE falling edge, 15/16 bpp
FPSHIFT2 falling edge to FPLINE falling edge, 4 bpp or 8 bpp
FPSHIFT2 falling edge to FPLINE falling edge, 15/16 bpp
FPLINE falling edge to FPSHIFT rising edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT rising edge, 15/16 bpp
FPSHIFT2, FPSHIFT pulse width high
18
4
14
16
16
18
note 6
note 6
note 7
note 7
18
16
2
2
1
238
240
240
242
FPSHIFT2, FPSHIFT pulse width low
FPDAT[7:0] setup to FPSHIFT2 rising, FPSHIFT falling edge
FPDAT[7:0] hold from FPSHIFT2 rising, FPSHIFT falling edge
1
1. Ts
= LCD pixel clock period. LCD pixel clock frequency is LCD pixel clock source divided by 1, 2, 3 or 4
(see REG[014h]).
2. t1
3. t4
4. t5
= t4 - 12
= [((REG[032h] bits [6:0]) + 1) × 8 + ((REG[034h] bits [4:0]) + 1) × 8]
= [((REG[034h] bits [4:0]) + 1) × 8 - 27] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 25] for 15/16 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 29] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 27] for 15/16 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 18] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 16] for 15/16 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 16] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 14] for 15/16 bpp color depth
5. t6
6. t9
7. t10
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
