Epson Research and Development
Page 5
Vancouver Design Center
List of Tables
Table 3-1: PC Card Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4-1: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4-2: Register/Memory Mapping for Typical Implementation . . . . . . . . . . . . . . . . . 16
List of Figures
Figure 2-1: PC Card Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
Figure 2-2: PC Card Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4-1: Typical Implementation of PC Card to S1D13506 Interface. . . . . . . . . . . . . . . . 14
Interfacing to the PC Card Bus
Issue Date: 01/02/06
S1D13506
X25B-G-005-03
EPSON [ EPSON COMPANY ]
