Epson Research and Development
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Vancouver Design Center
10.2.1 Write Blit with ROP
The Write Blit increases the speed of transferring data from system memory to the display
buffer.
The Write Blit with ROP fills a specified area of the display buffer with data supplied by
the CPU. This blit is typically used to copy a bitmap image from system memory to the
display buffer. The Write Blit supports all 16 ROPs, although the most frequent ROP is
ROP 0Ch (Copy Source into Destination). It also supports both Destination Linear and
Destination Rectangular modes.
The Write Blit requires the CPU to provide data. The blit engine expects to receive a certain
number of WORDS. For 15/16 bpp color depths, the number of WORDS is the same as the
number of pixels due to the fact that each pixel is one WORD wide. The number of WORD
writes the blit engine expects is calculated using the following formula.
nWORDS
= nPixels
= BlitWidth × BlitHeight
For 8 bpp color depths, the formula must take into consideration that the blit engine accepts
only WORD accesses and each pixel is one BYTE. The blit engine needs to know whether
the first pixel of a line is stored in the low byte or high byte. This is determined by bit 0 of
the Source Start Address Register 0 (REG[104h]). If the Source Phase is 1 (bit 0 of the
Source Start Address Register 0 is set), the first pixel of each line is in the high byte of the
WORD and the contents of the low byte are ignored. If the Source Phase is 0, the first pixel
is in the low byte and the second pixel is in the high byte. Depending on the Source Phase
and the Blit Width, the last WORD may contain only one pixel. In this case it is always in
the low byte. The number of WORD writes the blit engine expects for 8 bpp color depths
is shown in the following formula.
nWORDS
= ((BlitWidth + 1 + SourcePhase) ÷ 2) × BlitHeight
Note
The blit engine counts WORD writes in the blit address space. This does not imply only
16-bit CPU instructions are acceptable. If a system is able to separate one DWORD
write into two WORD writes, then 32-bit CPU instructions are acceptable. Otherwise,
two back to back 16-bit CPU instructions are required.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
EPSON [ EPSON COMPANY ]
