Page 212
Epson Research and Development
Vancouver Design Center
17 MediaPlug Interface
Winnov's MediaPlug Slave interface has been incorporated into the S1D13506. The
MediaPlug Slave follows the Specification For Winnov MediaPlug Slave, Local module,
Document Rev 0.3 with the following exceptions.
17.1 Revision Code
The MediaPlug Slave Revision Code can be determined by reading bits 11:8 of the LCMD
register. The revision code for this implementation is 0011b.
17.2 How to enable the MediaPlug Slave
The MediaPlug Slave interface uses the upper eight pins of the LCD data bus
(FPDAT[15:8]) for the data bus, clock, and control lines. When pin MD13 is high at the
rising edge of RESET#, FPDAT[15:8] are dedicated to the MediaPlug interface.
Table 17-1: MediaPlug Interface Pin Mapping
S1D13506
Pin Names
IO Type
MediaPlug I/F
FPDAT8
O
I
VMPLCTL
VMPRCTL
VMPD0
FPDAT9
FPDAT10
FPDAT11
FPDAT12
FPDAT13
FPDAT14
FPDAT15
DRDY or MA11
IO
IO
IO
IO
O
VMPD1
VMPD2
VMPD3
VMPCLK
VMPCLKN
VMPEPWR
O
O
Note
If MediaPlug is enabled, any 16-bit LCD panel must use an external circuit to support
FPDAT[15:8].
Either pin MA11 or pin DRDY can be configured as the MediaPlug power control output,
VMPEPWR. This is selected by the states of MD14, MD7, MD6 at the rising edge of
RESET# - see Table 5-6:, “Summary of Power-On/Reset Options,” on pag e39.
VMPEPWR is controlled by bit 1 of the MediaPlug LCMD register.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
