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S1D13506 参数 Datasheet PDF下载

S1D13506图片预览
型号: S1D13506
PDF下载: 下载PDF文件 查看货源
内容描述: S1D13506彩色LCD / CRT / TV控制器 [S1D13506 Color LCD/CRT/TV Controller]
分类和应用: 电视控制器
文件页数/大小: 696 页 / 5934 K
品牌: EPSON [ EPSON COMPANY ]
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Page 190  
Epson Research and Development  
Vancouver Design Center  
13.3 Filters  
When displaying computer images on a TV, several image distortions are likely to arise:  
• cross-luminance distortion.  
• cross-chrominance distortion.  
• flickering.  
These distortions are caused by the high-resolution nature of computer images which  
typically contain sharp color transitions, and sharp luminance transitions (e.g., high  
contrast one pixel wide lines and fonts, window edges, etc.). Three filters are available to  
reduce these distortions.  
13.3.1 Chrominance Filter (REG[05Bh] bit 5)  
The chrominance filter adjusts the color of the TV by limiting the bandwidth of the chromi-  
nance signal (reducing cross-luminance distortion). This reduces the “ragged edges” seen  
at boundaries between sharp color transitions. This filter is controlled using REG[05Bh]  
bit 5 and is most useful for composite video output.  
13.3.2 Luminance Filter (REG[05Bh] bit 4)  
The luminance filter adjusts the brightness of the TV by limiting the bandwidth of the  
luminance signal (reducing cross-chrominance distortion). This reduces the “rainbow-like”  
colors at boundaries between sharp luminance transitions. This filter is controlled using  
REG[05Bh] bit 4 and is most useful for composite video output.  
13.3.3 Anti-flicker Filter (REG[1FCh] bits [2:1])  
The “flickering” effect seen on interlaced displays is caused by sharp vertical image transi-  
tions that occur over one line (1 vertical pixel). For example, one pixel high lines, edges of  
window boxes, etc. Flickering occurs because these high resolution lines are effectively  
displayed at half the refresh frequency due to interlacing. The anti-flicker filter averages  
adjacent lines on the TV display to reduce flickering. This filter is controlled using the  
Display Mode register (REG[1FCh] bits [2:1]).  
S1D13506  
X25B-A-001-10  
Hardware Functional Specification  
Issue Date: 01/02/06  
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