EM48BM1684LBB
Extended Mode Register Set ( EMRS )
The Extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA1 ( The DDR
SDRAM should be in all bank precharge with CKE already prior to writing into the extended mode register. ) The
state of address pins A0-A10 and BA1 in the same cycle as /CS, /RAS, /CAS, and /WE going low is written in the
extended mode register. The mode register contents can be changed using the same command and clock cycle
requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable.
High on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper
EMRS operation.
BA1 BA0
A11
0
A10
0
A9
0
A8
0
A7
0
A6
A5
A4
0
A3
0
A2
A1
A0
1
0
DS
PASR
Self Refresh Coverage A2 A1 A0
All Banks
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Two Banks (BA1=0)
One Bank (BA0=BA1=0)
Reserved
Reserved
Reserved
Reserved
Reserved
Driver Strength
full
A6
A5
0
0
0
1
1
1/2 Strength
1/4 Strength
Reserved
1
0
1
BA1
MRS
0
1
Normal
EMRS
Nov. 2010
www.eorex.com
14/22
EOREX [ EOREX CORPORATION ]
