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EM482M3244VBC-8FE 参数 Datasheet PDF下载

EM482M3244VBC-8FE图片预览
型号: EM482M3244VBC-8FE
PDF下载: 下载PDF文件 查看货源
内容描述: 256MB ( 2M × 4Bank × 32 )同步DRAM [256Mb (2M】4Bank】32) Synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 19 页 / 1127 K
品牌: EOREX [ EOREX CORPORATION ]
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eorex  
Preliminary  
EM488M3244VBC  
AC Operating Test Characteristics (Continued)  
(VDD=3.3V±0.3V, TA=0°C ~70°C, -25°C ~ +85°C)  
-7.5  
Symbol  
tRC  
Parameter  
Units  
ns  
Min.  
67.5  
Max.  
ACTIVE to ACTIVE Command  
Period (Note 6)  
ACTIVE to PRECHARGE  
Command Period (Note 6)  
tRAS  
tRP  
45  
22.5  
22.5  
15  
100K  
ns  
PRECHARGE to ACTIVE  
Command Period (Note 6)  
ns  
ACTIVE to READ/WRITE Delay  
Time (Note 6)  
tRCD  
tRRD  
tCCD  
ns  
ACTIVE(one) to ACTIVE(another)  
Command (Note 6)  
ns  
READ/WRITE Command to  
READ/WRITE Command  
1
CLK  
Date-in to PRECHARGE  
Command  
tDPL  
tBDL  
tROH  
tREF  
2
CLK  
CLK  
Date-in to BURST Stop Command  
1
3
2
Data-out to High  
Impedance from  
PRECHARGE Command  
CL=3  
CL=2  
CLK  
ms  
Refresh Time (4,096 cycle)  
64  
* All voltages referenced to VSS.  
Note 6: These parameters account for the number of clock cycles and depend on the operating frequency  
of the clock, as follows:  
The number of clock cycles = Specified value of timing/clock period (Count Fractions as a whole  
number)  
Recommended Power On and Initialization  
The following power on and initialization sequence guarantees the device is preconditioned to each user’s  
specific needs. (Like a conventional DRAM) During power on, all VDD and VDDQ pins must be built up  
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on  
voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. (CLK signal started at same  
time)  
After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the  
precharge command.  
To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be  
held high during the initial pause period. Once all banks have been precharged, the Mode Register Set  
Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR)  
are also required, and these may be done before or after programming the Mode Register.  
May. 2007  
www.eorex.com  
8/19  
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