eorex
Preliminary
EM488M3244VBC
Pin Description (Simplified)
Pin
J1
Name
CLK
Function
(System Clock)
Master clock input (Active on the positive rising edge)
(Chip Select)
J8
J2
/CS
Selects chip when active
(Clock Enable)
Activates the CLK when “H” and deactivates when “L”.
CKE should be enabled at least one cycle prior to new
command. Disable input buffers for power down in standby.
(Address)
CKE
Row address (A0 to A11) is determined by A0 to A11 level at
the bank active command cycle CLK rising edge.
CA (CA0 to CA8) is determined by A0 to A8 level at the read or
write command cycle CLK rising edge.
And this column address becomes burst access start address.
A10 defines the pre-charge mode. When A10= High at the
pre-charge command cycle, all banks are pre-charged.
But when A10= Low at the pre-charge command cycle, only the
bank that is selected by BA is pre-charged.
(Bank Address)
Selects which bank is to be active.
(Row Address Strobe)
Latches Row Addresses on the positive rising edge of the CLK
with /RAS “L”. Enables row access & pre-charge.
(Column Address Strobe)
G8,G9,F7,F3,G1,
G2,G3,H1,H2,J3,
G7,H9
A0~A11
J7,H8
J9
BA0,BA1
/RAS
K7
/CAS
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Write Enable)
K8
/WE
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Data Input/Output Mask)
K9,K1,F8,F2
DQM0~DQM3
DQM controls I/O buffers.
R8,N7,R9,N8,P9,
M8,M7,L8,L2,M3,
M2,P1,N2,R1,N3,
R2,E8,D7,D8,B9,
C8,A9,C7,A8,A2,
C3,A1,C2,B1,D2,
D3,E2
(Data Input/Output)
DQ pins have the same function as I/O pins on a conventional
DRAM.
DQ0~DQ31
VDD/VSS
A7,F9,L7,R7/
A3,F1,L3,R3
(Power Supply/Ground)
VDD and VSS are power supply pins for internal circuits.
B2,B7,C9,D9,E1,
L1,M9,N9,P2/B8,
B3,C1,D1,E9,L9,
M1,N1,P8
(Power Supply/Ground)
VDDQ and VSSQ are power supply pins for the output buffers.
VDDQ/VSSQ
(No Connection)
This pin is recommended to be left No Connection on the
device.
E3,E7,H3,H7,K2,
K3
NC
May. 2007
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