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EM47FM3288SBA-125 参数 Datasheet PDF下载

EM47FM3288SBA-125图片预览
型号: EM47FM3288SBA-125
PDF下载: 下载PDF文件 查看货源
内容描述: [16Gb (64M×8Bank×32) Double DATA RATE 3 Stack SDRAM]
分类和应用: 动态存储器
文件页数/大小: 40 页 / 1121 K
品牌: EOREX [ EOREX CORPORATION ]
 浏览型号EM47FM3288SBA-125的Datasheet PDF文件第18页浏览型号EM47FM3288SBA-125的Datasheet PDF文件第19页浏览型号EM47FM3288SBA-125的Datasheet PDF文件第20页浏览型号EM47FM3288SBA-125的Datasheet PDF文件第21页浏览型号EM47FM3288SBA-125的Datasheet PDF文件第23页浏览型号EM47FM3288SBA-125的Datasheet PDF文件第24页浏览型号EM47FM3288SBA-125的Datasheet PDF文件第25页浏览型号EM47FM3288SBA-125的Datasheet PDF文件第26页  
EM47FM3288SBA  
AC Operating Test Characteristics  
(VDD, VDDQ=1.5V±0.075V)  
-125  
(DDR3-1600)  
-150  
(DDR3-1333)  
Speed Bin  
Notes  
20,21  
Symbol  
Units  
nCK  
CL-nRCD-nRP  
11-11-11  
9-9-9  
Parameter  
Min.  
Max.  
Min.  
1
Max.  
Timing of REF command to power-  
tREFPDEN  
1
-
-
down entry  
Timing of MRS command to power-  
down entry  
tMOD  
(min)  
tMOD  
(min)  
tMRSPDEN  
-
-
-
-
-
-
tCPDED  
Command pass disable delay  
1
1
nCK  
nCK  
Timing of ACT command to power-  
down entry  
tACTPDEN  
1
1
20  
20  
Timing of PRE command to power-  
down entry  
tPRPDEN  
1
-
1
-
nCK  
Timing of RD/RDA command to  
power-down entry  
RL + 4  
+1  
RL + 4  
+ 1  
tRDPDEN  
tAON  
-
-
nCK  
ps  
RTT turn-on  
-225  
225  
8.5  
-250  
250  
8.5  
7
8
Asynchronous RTT turn-on delay  
(Power-down with DLL frozen)  
tAONPD  
2
2
ns  
RTT_Nom and RTT_WR turn-off time  
from ODTLoff reference  
tCK  
(avg)  
tAOF  
tAOFPD  
ODTH4  
ODTH8  
tADC  
0.3  
2
0.7  
8.5  
-
0.3  
2
0.7  
8.5  
-
Asynchronous RTT turn-off delay  
(Power-down with DLL frozen)  
ns  
ODT high time without write command  
or with write command and BC4  
4
4
nCK  
nCK  
ODT high time with write command  
and BL8  
6
-
6
-
tCK  
(avg)  
RTT dynamic change skew  
0.3  
0.7  
0.3  
0.7  
tZQinit  
tZQoper  
tZQCS  
Power-up and reset calibration time  
Normal operation full calibration time  
Normal operation short calibration time  
512  
256  
64  
-
-
-
512  
256  
64  
-
-
-
nCK  
nCK  
nCK  
23  
3
First DQS pulse rising edge after write  
leveling mode is programmed  
tWLMRD  
40  
25  
-
-
40  
-
-
nCK  
nCK  
DQS./DQS delay after write leveling  
mode is programmed  
tWLDQSEN  
25  
3
RL +  
CCD/2 +  
2nCK-W  
L
RL + tCCD/2  
+
2nCK-WL  
Read to write command delay  
(BC4MRS, BC4OTF)  
t
tRTW  
-
-
RL +  
CCD/2 +  
2nCK-W  
L
RL + tCCD/2  
+
2nCK-WL  
Read to write command delay  
(BL8MRS, BL8OTF)  
t
tRTW  
-
-
-
-
Active to read with auto precharge  
command delay  
tRCD  
min  
tRAP  
tRCD min  
Jul. 2012  
22/40  
www.eorex.com  
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