EM47FM0888SBA
AC Operating Test Characteristics
VDD/VDDQ = 1.5V±0.075V
Speed Bin
-150 (DDR3-1333)
-187 (DDR3-1066)
Symbol
Units Notes
CL-nRCD-nRP
Parameter
9-9-9
7-7-7
Min.
165
Max.
-
Min.
195
Max.
-
Write leveling setup time from
rising CK,/CK crossing to rising
DQS,/DQS crossing
ps
ps
tWLS
tWLH
Write leveling hold time from
rising DQS,/DQS crossing to
rising CK,/CK crossing
165
-
195
-
Write leveling output delay
Write leveling output error
Absolute clock period
0
0
7.5
2
tCK (avg)max+
tJIT (per)max
0
0
9
2
ns
ns
ps
tWLO
tWLOE
tCK (avg)min+
tJIT(per)min
tCK (avg)min+
tJIT (per)min
tCK (avg)max+
tJIT (per)max
tCK (abs)
tCK
(avg)
Absolute clock high pulse width
0.43
0.43
-
-
0.43
0.43
-
-
30
tCH (abs)
tCL (abs)
tCK
(avg)
Absolute clock low pulse width
Clock period jitter
31
-70
-60
70
60
-80
-70
80
70
ps
tJIT (per)
Clock period jitter during DLL
locking period
ps
tJIT (per,lck)
Cycle to cycle period jitter
-
-
140
120
-
-
160
140
ps
ps
tJIT (cc)
Cycle to cycle period jitter during
DLL locking period
tJIT (cc,lck)
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
-103
-122
-136
-147
-155
-163
-169
-175
103
122
136
147
155
163
169
175
-118
-140
-155
-168
-177
-186
-193
-200
118
140
155
168
177
186
193
200
ps
ps
ps
ps
ps
ps
ps
ps
tERR (2per)
tERR (3per)
tERR (4per)
tERR (5per)
tERR (6per)
tERR (7per)
tERR (8per)
tERR (9per)
Cumulative error across 10
cycles
-180
-184
-188
180
184
188
-205
-210
-215
205
210
215
ps
ps
ps
tERR (10per)
tERR (11per)
tERR (12per)
Cumulative error across 11
cycles
Cumulative error across 12
cycles
Cumulative error across
tERR (nper)min=(1+0.68ln(n))*tJIT (per)min
tERR (nper)max=(1+0.68ln(n))*tJIT (per)max
ps
32
tERR (nper)
n= 13,14,… 49,50 cycles
Jul. 2012
20/39
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