EM47FM0888SBA
AC Operating Test Characteristics
VDD/VDDQ = 1.5V±0.075V
-150
(DDR3-1333)
-187
Speed Bin
(DDR3-1066)
Units Notes
7-7-7
Symbol
CL-nRCD-nRP
9-9-9
Parameter
Min.
0.18
Max.
Min.
0.2
Max.
-
DQS falling edge hold time from
tCK
(avg)
-
29
tDSH
rising CK
DQS falling edge setup time to rising
CK
tCK
(avg)
0.18
0.45
0.40
0.40
-
0.2
-
29
tDSS
tCK
(avg)
DQS input low pulse width
DQS output high time
0.55
0.45
0.40
0.40
0.55
26,28
12,13
12,13
tDQSL
tQSH
tCK
(avg)
-
-
-
-
tCK
(avg)
DQS output low time
tQSL
tMRD
tMOD
Mode register set command cycle
4
-
-
-
4
-
-
-
nCK
ns
15
12
15
12
Mode register set command update
delay
nCK
tCK
(avg)
Read preamble time
Read postamble time
Write preamble time
0.9
0.3
0.9
-
-
-
0.9
0.3
0.9
-
-
-
13,19
11,13
1
tRPRE
tRPST
tWPRE
tWPST
tCK
(avg)
tCK
(avg)
tCK
(avg)
Write postamble time
Write recovery time
0.3
15
-
-
0.3
15
-
-
1
ns
tWR
Auto precharge write recovery +
precharge time
nCK
tDAL(min)
WR + roundup[tRP / tCK(avg)
Multi purpose register recovery time
1
7.5
4
-
-
-
-
-
1
7.5
4
-
-
-
-
-
nCK
ns
22
18
tMPRR
tWTR
Internal write to read command delay
nCK
ns
7.5
4
7.5
4
Internal read to precharge command
delay
tRTP
nCK
Minimum CKE low width for self-
refresh entry to exit
tCKE (min)
tCKE (min)
-
-
nCK
tCKESR
tCKSRE
+1
+1
10
5
-
-
-
-
10
5
-
-
-
-
ns
nCK
ns
Valid clock requirement after self-
refresh entry or power-down entry
10
5
10
5
Valid clock requirement before self-
refresh exit or power-down exit
tCKSRX
nCK
Jul. 2012
17/39
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EOREX [ EOREX CORPORATION ]
