EM47FM0888SBA
AC Operating Test Characteristics
VDD/VDDQ = 1.5V±0.075V
-125
(DDR3-1600)
-150
Speed Bin
(DDR3-1333)
Units Notes
9-9-9
Symbol
CL-nRCD-nRP
11-11-11
Parameter
Min.
8
Max.
Min.
8
Max.
Minimum clock cycle, DLL-off mode
Average CK high/low level width
-
-
ns
ns
6
tCK
0.47
6
0.53
0.47
6
0.53
tCH, tCL (AVG)
-
-
-
-
-
-
ns
Active bank A to active bank B
command period
tRRD
4
4
nCK
ns
Four Activate Window
30
30
tFAW
Address and Control input hold time
(VIH/VIL(DC100) levels)
tIH(base)
DC100
120
45
-
-
-
-
-
-
-
140
65
-
-
-
-
-
-
-
ps
ps
ps
ps
ps
ps
ps
16
16
Address and Control input setup time
(VIH/VIL(AC175) levels)
tIS(base)
AC175
Address and Control input setup time
(VIH/VIL(AC150) levels)
tIS(base)
AC150
45+125
45
65+150
65
16,24
17
DQ and DM input hold time
(VIH/VIL(DC) levels)
tDH(base)
tDS(base)
tIPW
DQ and DM input setup time
(VIH/VIL(AC) levels)
10
10
17
Address and control input pulse width
for each input
560
360
620
400
25
DQ and DM input pulse width for
each input
25
tDIPW
DQ high impedance time
DQ low impedance time
DQS,/DQS high impedance time
RL+BL/2 reference
-
225
225
-
250
250
ps
ps
13,14
13,14
tHZ(DQ)
tLZ(DQ)
-450
-500
-
225
-
250
ps
ps
13,14
tHZ(DQS)
DQS,/DQS low impedance time
RL-1 reference
-450
-
225
100
-500
-
250
125
13,14
12,13
tLZ(DQS)
DQS,/DQS to DQ skew per group,
per access
ps
tDQSQ
/CAS to /CAS command delay
4
-
-
4
-
-
nCK
tCCD
tQH
tCK
(avg)
DQ output hold time from DQS, /DQS
0.38
0.38
12,13
12,13
DQS,/DQS rising edge output access
time from rising CK,/CK
-225
-0.27
0.45
225
0.27
0.55
-255
-0.25
0.45
255
0.25
0.55
ps
tDQSCK
tDQSS
tDQSH
DQS latch rising transitions to
associated clock edges
tCK
(avg)
tCK
(avg)
DQS input high pulse width
27,28
Jul. 2012
16/39
www.eorex.com
EOREX [ EOREX CORPORATION ]
