EM44CM0884LBA
Output Drive Strength
The output drive strength is defined by bit A1. Normal drive strength outputs are specified to be SSTL_18.
Programming bit A1 = 0 selects normal (100 %) drive strength for all outputs.
Programming bit A1 = 1 will reduce all outputs to approximately 60 % of the SSTL_18 drive strength.
This option is intended for the support of the lighter load and/or point-to-point environments.
Single-ended and Differential Data Strobe Signals
EMRS
Strobe Function Matrix
/RDQS DQS
Signals
A11
A10
RDQS
DM
/DQS
(/RDQS Enable) (/DQS Enable)
0 (Disable)
0 (Disable)
1 (Enable)
0 (Enable)
1 (Disable)
0 (Enable)
DM
Hi-Z
Hi-Z
DQS
DQS
/DQS
Hi-Z
Differential DQS signal
Single-ended DQS signal
Differential DQS signal
DM
RDQS
/RDQS DQS
Hi-Z DQS
/DQS
1 (Enable)
1 (Disable)
RDQS
Hi-Z
Single-ended DQS signal
Output Disable (Qoff)
Under normal operation, the DRAM outputs are enabled during Read operation for driving data Qoff bit in the
EMRS(1) is set to (0). When the Qoff bit is set to 1, the DRAM outputs will be disabled. Disabling the DRAM
outputs allows users to measure IDD currents during Read operations, without including the output buffer
current.
Dec. 2014
25/28
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EOREX [ EOREX CORPORATION ]
