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EM44CM0884LBA_15 参数 Datasheet PDF下载

EM44CM0884LBA_15图片预览
型号: EM44CM0884LBA_15
PDF下载: 下载PDF文件 查看货源
内容描述: [Double DATA RATE 2 SDRAM]
分类和应用: 动态存储器
文件页数/大小: 28 页 / 778 K
品牌: EOREX [ EOREX CORPORATION ]
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EM44CM0884LBA  
Extended Mode Register Set EMRS(1 )  
The EMRS (1) is written by asserting low on /CS, /RAS, /CAS, /WE,BA1 and high on BA0 ( The DDR2 should  
be in all bank pre-charge with CKE already prior to writing into the extended mode register. ) The extended  
mode register EMRS(1) stores the data for enabling or disabling the DLL, output driver strength, additive  
latency, OCD program, ODT, DQS and output buffers disable, RQDS and RDQS enable. The default value of  
the extended mode register EMRS(1) is not defined, therefore the extended mode register must be written after  
power-up for proper operation. The mode register set command cycle time (tMRD) must be satisfied to complete  
the write operation to the EMRS(1). Mode register contents can be changed using the same command and  
clock cycle requirements during normal operation when all banks are in pre-charge state.  
BA1  
0
BA2  
0
BA0  
1
A13  
0
A12  
Qoff  
A11  
A10  
A9  
A8  
A7  
A6  
Rtt  
A5  
A4  
A3  
A2  
Rtt  
A1  
A0  
RDQS  
/DQS  
OCD program  
Additive latency  
DIC  
DLL  
DLL  
A0  
(Output Buffer)  
Enabled  
Qoff  
A12  
RDQS  
enable  
A11  
/DQS  
A10  
0
Enable  
Disable  
0  
1  
0
1
Enable  
Disable  
Disable  
Enable  
0
Disabled  
1
1
Output Driver  
A1  
Impedance Control  
Normal (100%)  
Weak (60%)  
0
1
OCD Calibration Program  
OCD Calibration mode exit  
A9 A8  
A7  
0
0
0
0
Drive (1)  
Drive (0)  
1
Rtt  
A6  
0
A2  
1
0  
ODT Disable  
0
1
0
1
0
1
0
1
1
Adjust mode (*1)  
75 ohm  
0
OCD Calibration default (*2)  
1
150 ohm  
1
50 ohm *  
1
*1:  
*2:  
e applied.  
When adjust mode is issued, AL from previously set value must b  
After setting to default, OCD mode needs to be exited by settin  
-
A7 to 000.  
g A9  
-
Refer to the section Off  
Chip Driver (OCD) impedance adjustment for detail  
information  
Additive Latency  
A5  
0
A4  
0
A3  
0
0
1
0
1
0
1
0
1
MRS Mode  
MRS  
BA1  
0
BA0  
0
1
0
0
2
0
1
EMRS(1)  
EMRS(2)  
0
1
3
0
1
1
0
4
1
0
EMRS(3) Reserved  
1
1
5
1
0
6
1
1
Reserved  
1
1
Note1. For DDR2-1066, the Rttmust be set to 50 ohm (A2 = 1 & A6 = 1).  
Note2. A13 is reserved for future use.  
Note3. BA2 is reserved for future use.  
Dec. 2014  
24/28  
www.eorex.com  
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