eorex
EM44AM1684LBA
Address input for Extended Mode Register Set ( EMRS(1) )
The EMRS (1) is written by asserting low on /CS, /RAS, /CAS, /WE,BA1 and high on BA0 ( The DDR2
should be in all bank pre-charge with CKE already prior to writing into the extended mode register. )
The extended mode register EMRS(1) stores the data for enabling or disabling the DLL, output driver
strength, additive latency,OCD program, ODT, DQS and output buffers disable, RQDS and RDQS enable.
The default value of the extended mode register EMRS(1) is not defined, therefore the extended mode
register must be written after power-up for proper operation.The mode register set command cycle time
(tMRD) must be satisfied to complete the write operation to the EMRS(1). Mode register contents can be
changed using the same command and clock cycle requirements during normal operation when all banks
are in pre-charge state.
BA1 BA0 A12 A11 A10
A9
A8
A7
A6
Rtt
A5
A4
AL
A3
A2
Rtt
A1
A0
RDQS /DQS
D.I.C
0
1
Q off
OCD Program
DLL
A12
0
DLL
A10
0
Q off
/ DQS
Rtt A6 A2
A0
0
Disabl
Disable
Enable
Enable
Disable
0
0
1
1
0
1
0
1
Enable
Output
Disable
1
1
75Ω
1
150Ω
50Ω
buffers
RDQS,
/RQDS
Output Driver
Impedence Control
A11
I/O
A1
Disable
Enable
0
1
Normal (100%)
Weak ( 60%)
0
1
onlyX8
OCD Operation
OCD calibration mode exit
Drive (1)
A9
0
A8 A7
Additive Latency
A5
0
A4
A3
0
0
0
1
0
1
0
1
0
0
1
0
0
0
1
1
0
0
1
1
0
1
0
1
Drive (0)
0
2
0
0
(Note 1)
1
3
0
1
Adjust mode
OCD Calibration default (Note 2)
1
4
1
0
Reserved
Reserved
Reserved
1
1
1
0
1
1
BA1
0
BA0
0
MRS Mode
Mode Register (MRS)
Note 1: When adjust mode is issued, AL from
previously set value must be applied.
Note 2: After setting to default, OCD mode needs
to be exited by setting A9 ~A7 to 000.
Refer to the chapter Off-Chip Driver (OCD)
Impedance Adjustment for detailed information.
0
1
Extended Mode Register / EMRS(1)
EMRS(2) * Reserved
1
0
1
1
EMRS(3) * Reserved
Jul. 2006
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