EN29LV160A
Table 12. AC CHARACTERISTICS
Read-only Operations Characteristics
Parameter
Symbols
Speed Options
Test
Description
Setup
JEDEC
Standard
-70
-90
Unit
Min
70
90
ns
Read Cycle Time
tAVAV
tRC
CE# = VIL
OE#= VIL
Max
Max
Max
Max
Max
Min
70
70
30
20
20
0
90
90
35
20
20
0
ns
ns
ns
ns
ns
ns
Address to Output Delay
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
tACC
tCE
tOE
tDF
Chip Enable To Output Delay
Output Enable to Output Delay
Chip Enable to Output High Z
Output Enable to Output High Z
OE#= VIL
tDF
Output Hold Time from
Addresses, CE# or OE#,
whichever occurs first
tOH
Notes:
For - 70
Vcc = 3.0V ± 5%
Output Load : 1 TTL gate and 30pF
Input Rise and Fall Times: 5ns
Input Rise Levels: 0.0 V to 3.0 V
Timing Measurement Reference Level, Input and Output: 1.5 V
For all others:
Vcc = 2.7V – 3.6V
Output Load: 1 TTL gate and 100 pF
Input Rise and Fall Times: 5 ns
Input Pulse Levels: 0.45 V to .8 x Vcc
Timing Measurement Reference Level, Input and Output: 0.8 V and .7 x Vcc
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
Output Valid
Outputs
Reset#
RY/BY#
0V
Figure 5. AC Waveforms for READ Operations
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
29
Rev. C, Issue Date: 2005/01/07
EON [ EON SILICON SOLUTION INC. ]
