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EN25S20-75WIP 参数 Datasheet PDF下载

EN25S20-75WIP图片预览
型号: EN25S20-75WIP
PDF下载: 下载PDF文件 查看货源
内容描述: 2兆位1.8V串行闪存与4K字节扇区制服 [2 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector]
分类和应用: 闪存
文件页数/大小: 34 页 / 564 K
品牌: EON [ EON SILICON SOLUTION INC. ]
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EN25S20  
OPERATING FEATURES  
Standard SPI Modes  
The EN25S20 is accessed through a SPI compatible bus consisting of four signals: Serial Clock (CLK),  
Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0  
(0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in  
Figure 3, concerns the normal state of the CLK signal when the SPI bus master is in standby and data  
is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the  
CLK signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the  
CLK. Data output on the DO pin is clocked out on the falling edge of CLK.  
Figure 3. SPI Modes  
Page Programming  
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and  
a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal  
Program cycle (of duration tPP).  
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed  
at a time (changing bits from 1 to 0) provided that they lie in consecutive addresses on the same page  
of memory.  
Sector Erase, Block Erase and Chip Erase  
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the  
bytes of memory need to have been erased to all 1s (FFh). This can be achieved a sector at a time,  
using the Sector Erase (SE) instruction, a block at a time using the Block Erase (BE) instruction or  
throughout the entire memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle  
(of duration tSE tBE or tCE). The Erase instruction must be preceded by a Write Enable (WREN)  
instruction.  
Polling During a Write, Program or Erase Cycle  
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE or  
CE ) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, tBE or tCE). The Write In  
Progress (WIP) bit is provided in the Status Register so that the application program can monitor its  
value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.  
Active Power, Stand-by Power and Deep Power-Down Modes  
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip  
Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal  
cycles have completed (Program, Erase, Write Status Register). The device then goes into the Stand-  
by Power mode. The device consumption drops to ICC1  
.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down  
Mode (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains  
in this mode until another specific instruction (the Release from Deep Power-down Mode and Read  
Device ID (RDI) instruction) is executed.  
This Data Sheet may be revised by subsequent versions  
or modifications due to changes in technical specifications.  
©2004 Eon Silicon Solution, Inc., www.eonssi.com  
6
Rev. H, Issue Date: 2011/11/07