欢迎访问ic37.com |
会员登录 免费注册
发布采购

EN25Q128-104FIP 参数 Datasheet PDF下载

EN25Q128-104FIP图片预览
型号: EN25Q128-104FIP
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆位串行闪存与4K字节扇区制服 [128 Megabit Serial Flash Memory with 4Kbyte Uniform Sector]
分类和应用: 闪存
文件页数/大小: 57 页 / 1077 K
品牌: EON [ EON SILICON SOLUTION INC. ]
 浏览型号EN25Q128-104FIP的Datasheet PDF文件第43页浏览型号EN25Q128-104FIP的Datasheet PDF文件第44页浏览型号EN25Q128-104FIP的Datasheet PDF文件第45页浏览型号EN25Q128-104FIP的Datasheet PDF文件第46页浏览型号EN25Q128-104FIP的Datasheet PDF文件第48页浏览型号EN25Q128-104FIP的Datasheet PDF文件第49页浏览型号EN25Q128-104FIP的Datasheet PDF文件第50页浏览型号EN25Q128-104FIP的Datasheet PDF文件第51页  
EN25Q128  
Table 11. AC Characteristics  
(Ta = - 40°C to 85°C or -40°C ~125°C; VCC = 2.7-3.6V)  
Symbol  
Alt  
Parameter  
Min  
D.C.  
Typ  
Max  
Unit  
MHz  
Serial Clock Frequency for:  
FAST_READ, PP, SE, BE, DP, RES, WREN,  
WRDI, WRSR  
-
104  
FR  
fC  
Serial Clock Frequency for:  
RDSR, RDID, Dual Output Fast Read  
D.C.  
D.C.  
-
-
80  
50  
MHz  
MHz  
Serial Clock Frequency for READ, Quad I/O Fast  
Read  
fR  
1
tCH  
Serial Clock High Time  
4
4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
1
tCL  
Serial Clock Low Time  
2
tCLCH  
Serial Clock Rise Time (Slew Rate)  
Serial Clock Fall Time (Slew Rate)  
CS# Active Setup Time (Relative to CLK)  
CS# Active Hold Time (Relative to CLK)  
CS# Not Active Setup Time (Relative to CLK)  
CS# Not Active Hold Time (Relative to CLK)  
0.1  
0.1  
5
V / ns  
V / ns  
ns  
2
tCHCL  
tSLCH  
tCHSH  
tSHCH  
tCHSL  
tCSS  
5
ns  
5
ns  
5
ns  
CS# High Time for read  
CS# High Time for program/erase  
15  
50  
ns  
ns  
tSHSL  
tCSH  
-
-
2
tDIS  
tHO  
tDSU  
tDH  
tV  
tSHQZ  
Output Disable Time  
-
0
-
-
-
-
-
-
-
-
6
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
tCLQX  
tDVCH  
tCHDX  
tCLQV  
Output Hold Time  
Data In Setup Time  
2
-
Data In Hold Time  
5
-
Output Valid from CLK  
-
8
-
3
tWHSL  
Write Protect Setup Time before CS# Low  
Write Protect Hold Time after CS# High  
CS# High to Deep Power-down Mode  
20  
100  
-
3
tSHWL  
-
2
tDP  
3
CS# High to Standby Mode without Electronic  
Signature read  
2
tRES1  
-
-
-
-
3
µs  
µs  
CS# High to Standby Mode with Electronic  
Signature read  
2
tRES2  
1.8  
tW  
Write Status Register Cycle Time  
Page Programming Time  
Sector Erase Time  
-
-
-
-
-
-
-
15  
0.8  
0.05  
0.2  
45  
-
50  
5
ms  
ms  
s
tPP  
tSE  
tBE  
tCE  
0.3  
2
Block Erase Time  
s
140  
28  
0
s
Chip Erase Time  
WIP = write operation  
Software Reset  
µs  
µs  
tSR  
Latency  
WIP = not in write operation  
-
Note: 1. tCH + tCL must be greater than or equal to 1/ fC  
2. Value guaranteed by characterization, not 100% tested in production.  
3. Only applicable as a constraint for a Write status Register instruction when Status Register Protect Bit is set at 1.  
This Data Sheet may be revised by subsequent versions  
or modifications due to changes in technical specifications.  
©2004 Eon Silicon Solution, Inc., www.eonssi.com  
47  
Rev. J, Issue Date: 2011/09/19  
 复制成功!