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EN25Q128-104FIP 参数 Datasheet PDF下载

EN25Q128-104FIP图片预览
型号: EN25Q128-104FIP
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆位串行闪存与4K字节扇区制服 [128 Megabit Serial Flash Memory with 4Kbyte Uniform Sector]
分类和应用: 闪存
文件页数/大小: 57 页 / 1077 K
品牌: EON [ EON SILICON SOLUTION INC. ]
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EN25Q128  
Figure 21. Deep Power-down Instruction Sequence Diagram  
Release from Deep Power-down and Read Device ID (RDI)  
Once the device has entered the Deep Power-down mode, all instructions are ignored except the  
Release from Deep Power-down and Read Device ID (RDI) instruction. Executing this instruction takes  
the device out of the Deep Power-down mode.  
Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature  
that is read by the Read Identifier (RDID) instruction. The old-style Electronic Signature is supported for  
reasons of backward compatibility, only, and should not be used for new designs. New designs should,  
instead, make use of the JEDEC 16-bit Electronic Signature, and the Read Identifier (RDID) instruction.  
When used only to release the device from the power-down state, the instruction is issued by driving  
the CS# pin low, shifting the instruction code “ABh” and driving CS# high as shown in Figure 22. After  
the time duration of t  
(See AC Characteristics) the device will resume normal operation and other  
RES1  
instructions will be accepted. The CS# pin must remain high during the t  
time duration.  
RES1  
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by  
driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device  
ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in  
Figure 23. The Device ID value for the EN25Q128 are listed in Table 5. The Device ID can be read  
continuously. The instruction is completed by driving CS# high.  
When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device  
was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is  
immediate. If the device was previously in the Deep Power-down mode, though, the transition to the  
Standby Power mode is delayed by t  
, and Chip Select (CS#) must remain High for at least t  
RES2  
RES2  
(max), as specified in Table 11. Once in the Stand-by Power mode, the device waits to be selected, so  
that it can receive, decode and execute instructions.  
Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep  
Power-down and Read Device ID (RDI) instruction always provides access to the 8bit Device ID of the  
device, and can be applied even if the Deep Power-down mode has not been entered.  
Any Release from Deep Power-down and Read Device ID (RDI) instruction while an Erase, Program or  
Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in  
progress.  
This Data Sheet may be revised by subsequent versions  
or modifications due to changes in technical specifications.  
©2004 Eon Silicon Solution, Inc., www.eonssi.com  
39  
Rev. J, Issue Date: 2011/09/19  
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