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EN63A0QI 参数 Datasheet PDF下载

EN63A0QI图片预览
型号: EN63A0QI
PDF下载: 下载PDF文件 查看货源
内容描述: 12A同步高度集成DC-DC PowerSoC [12A Synchronous Highly Integrated DC-DC PowerSoC]
分类和应用:
文件页数/大小: 24 页 / 1511 K
品牌: ENPIRION [ ENPIRION, INC. ]
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EN63A0QI  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Falling Edge Deglitch Delay After  
Output Crossing 90% level.  
FSW=1.2 MHz  
POK Deglitch Delay  
213  
µs  
VPOK Logic Low level  
VPOK Logic high level  
With 4mA Current Sink into POK Pin  
0.4  
V
V
VIN  
94  
POK Internal pull-up  
resistor  
kΩ  
With 2 to 4 Converters in Parallel,  
the Difference Between Nominal  
and Actual Current Levels.  
Current Balance  
+/-10  
%
IOUT  
VIN<50mV; RTRACE< 10 m,  
Iload= # Converter * IMAX  
tRISE [ms] = CSS [nF] x 0.065;  
10nF CSS 30nF;  
(Note 5 and Note 6)  
TRISE  
VOUT Rise Time  
Accuracy  
-25  
+25  
%
(Note 4)  
ENABLE Logic High  
ENABLE Logic Low  
ENABLE Pin Current  
VENABLE_HIGH 2.5V VIN 6.6V;  
1.2  
0
VIN  
0.8  
V
V
VENABLE_LOW  
IEN  
VIN = 6.6V  
50  
µA  
M/S Ternary Pin Logic  
Low  
VT-LOW  
Tie M/S Pin to GND  
0
0.7  
1.4  
V
V
V
M/S Ternary Pin Logic  
Float  
VT-FLOAT  
VT-HIGH  
M/S Pin is Open  
1.1  
1.8  
M/S Ternary Pin Logic  
Hi (Note 7)  
Pull Up to VIN through an external  
resistor REXT . Refer to Figure 7.  
2.5V VIN 4V, REXT = 15k  
4V < VIN 6.6V, REXT = 51k  
117  
88  
Ternary Pin Input  
Current  
ITERN  
µA  
Binary Pin Logic Low  
Threshold  
VB-LOW  
VB-HIGH  
ENABLE, S_IN  
ENABLE, S_IN  
0.8  
V
V
Binary Pin Logic High  
Threshold  
1.8  
2.0  
S_OUT Low Level  
S_OUT High Level  
VS_OUT_LOW  
VS_OUT_HIGH  
0.4  
V
V
Note 3: POK threshold when VOUT is rising is nominally 92%. This threshold is 90% when VOUT is falling. After crossing  
the 90% level, there is a 256 clock cycle (~213µs at 1.2 MHz) delay before POK is de-asserted. The 90% and 92% levels  
are nominal values. Expect these thresholds to vary by 3%.  
Note 4: Parameter not production tested but is guaranteed by design.  
Note 5: Rise time calculation begins when AVIN > VUVLO and ENABLE = HIGH.  
Note 6: VOUT Rise Time Accuracy does not include soft-start capacitor tolerance..  
Note 7: M/S pin is ternary. Ternary pins have three logic levels: high, float, and low. This pin is meant to be strapped to  
VIN through an external resistor, strapped to GND, or left floating. The state cannot be changed while the device is on.  
Enpirion 2012 all rights reserved, E&OE  
Enpirion Confidential  
www.enpirion.com, Page 6  
07077  
May 9, 2012  
Rev: C  
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