EN6337QI
Recommendation 6: AVIN is the power supply
for the internal small-signal control circuits. It
should be connected to the input voltage at a
quiet point. In Figure 7 this connection is made
at the input capacitor close to the VIN
connection.
Recommendation 8: The VOUT sense point
should be just after the last output filter
capacitor. Keep the sense trace as short as
possible in order to avoid noise coupling into
the control loop.
Recommendation 9: Keep RA, CA, and RB
close to the VFB pin (see Figures 6 and 7).
The VFB pin is a high-impedance, sensitive
node. Keep the trace to this pin as short as
possible. Whenever possible, connect RB
directly to the AGND pin instead of going
through the GND plane.
Recommendation 7: The layer 1 metal under
the device must not be more than shown in
Figure 7. See the section regarding exposed
metal on bottom of package. As with any
switch-mode DC/DC converter, try not to run
sensitive signal or control lines underneath the
converter package on other layers.
Design Considerations for Lead-Frame Based Modules
several small pads being exposed on the
bottom of the package.
Exposed Metal on Bottom of Package
Lead frames offers many advantages in
thermal performance, in reduced electrical lead
resistance, and in overall foot print. However,
they do require some special considerations.
Only the large thermal pad and the perimeter
pads are to be soldered to the PC board. The
PCB top layer under the EN6337QI should be
clear of any metal except for the large thermal
pad. The “grayed-out” region in Figure 8
represents the area that should be clear of any
metal (traces, vias, or planes), on the top layer
of the PCB.
In the assembly process lead frame
construction requires that, for mechanical
support, some of the lead-frame cantilevers be
exposed at the point where wire-bond or
internal passives are attached. This results in
VIN copper covered by
soldermask acceptable near
or under this exposed pad.
Figure 8: Lead-Frame Exposed Metal. Grey area highlights exposed metal below which
there should not be any metal (traces, vias, or planes) on the top layer of PCB.
©Enpirion 2011 all rights reserved, E&OE
15
www.enpirion.com
05800
6/17/2011
Rev: B
ENPIRION [ ENPIRION, INC. ]
