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EN6337QI 参数 Datasheet PDF下载

EN6337QI图片预览
型号: EN6337QI
PDF下载: 下载PDF文件 查看货源
内容描述: 3A电压模式同步降压PWM DC -DC转换器集成电感器 [3A Voltage Mode Synchronous Buck PWM DC-DC Converter with Integrated Inductor]
分类和应用: 转换器电感器
文件页数/大小: 17 页 / 417 K
品牌: ENPIRION [ ENPIRION, INC. ]
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EN6337QI  
device. Additional bulk output capacitance  
beyond the above recommendations can be  
used on the output node of the EN6337QI as  
long as the bulk capacitors are far enough from  
the VOUT sense point such that they don’t  
interfere with the control loop operation.  
Typical PWM Ripple Voltages  
Typical Output Ripple (mVp-p)  
(as measured on EN6337QI  
Evaluation Board)*  
Output Capacitor  
Configuration  
1 x 47 µF  
25  
14  
47 µF + 10 µF  
In some cases modifications to the  
compensation or output filter capacitance may  
be required to optimize device performance  
such as transient response, ripple, or hold-up  
time. The EN6337QI provides the capability to  
modify the control loop response to allow for  
customization for such applications. For more  
information, contact Enpirion Applications  
Engineering support.  
* Note: 20 MHz BW limit  
Recommended Output Capacitors  
Description  
MFG  
P/N  
Murata  
GRM31CR60J476ME19L  
47uF, 6.3V, 20%  
X5R, 1206  
(1 or 2 capacitors needed)  
Taiyo  
Yuden  
JMK316BJ476ML-T  
10uF, 10V, 10%  
X5R, 1206  
(Optional 1 capacitor in  
parallel with 47uF above)  
Murata  
GRM31CR71A106KA01L  
Taiyo  
Yuden  
LMK316BJ226ML-T  
Power-Up Sequencing  
For best LLM performance, we recommend  
using just 2x47uF capacitors mentioned in the  
above table, and no 10uF capacitor.  
During power-up, ENABLE should not be  
asserted before PVIN, and PVIN should not be  
asserted before AVIN. Tying all three pins  
together meets these requirements.  
The VOUT sense point should be just after the  
last output filter capacitor right next to the  
Thermal Considerations  
The Enpirion EN6337QI DC-DC converter is  
packaged in a 7x4x1.85mm 38-pin QFN  
package. The QFN package is constructed  
with copper lead frames that have exposed  
thermal pads. The recommended maximum  
junction temperature for continuous operation  
is 125°C. Continuous operation above 125°C  
will reduce long-term reliability. The device has  
a thermal overload protection circuit designed  
to shut it off at a junction temperature specified  
in the Electrical Characteristics Table.  
The junction temperature, TJ, is calculated from  
the ambient temperature, TA, the device power  
dissipation, PD, and the device junction-to-  
ambient thermal resistance, θJA in °C/W, as  
follows:  
TJ = TA + (PD) (θJA)  
The junction temperature, TJ, can also be  
expressed in terms of the device case  
temperature, TC, and the device junction-to-  
case thermal resistance, θJC in °C/W, as  
follows:  
The silicon is mounted on a copper thermal  
pad that is exposed at the bottom of the  
package. The thermal resistance from the  
silicon to the exposed thermal pad is very low.  
In order to take advantage of this low  
resistance, the exposed thermal pad on the  
package should be soldered directly on to a  
copper ground pad on the printed circuit board  
(PCB). The PCB then acts as a heat sink. In  
order for the PCB to be an effective heat sink,  
the device thermal pad should be coupled to  
copper ground planes or special heat sink  
structures designed into the PCB (refer to the  
Layout Recommendations section).  
TJ = TC + (PD) (θJC)  
The device case temperature, TC, is the  
temperature at the center of the exposed  
thermal pad at the bottom of the package.  
The device junction-to-ambient and junction-to-  
case thermal resistances, θJA and θJC, are  
shown in the Thermal Characteristics table on  
page 3. The θJC is a function of the device and  
the QFN package design. The θJA is a function  
of θJC and the user’s system design  
parameters  
that  
include  
the  
thermal  
effectiveness of the customer PCB and airflow.  
©Enpirion 2011 all rights reserved, E&OE  
13  
www.enpirion.com  
05800  
6/17/2011  
Rev: B