R
EM3027
7
Serial communication
Depending on the EM3027 version, the serial communi-
cation is performed in I2C or SPI mode.
When the “Transmission START” is detected, a copy of
the content of the addressed Watch-, Alarm-, Timer- and
Temperature-register is stored into a cache memory.
Data for a following read access are provided from this
cache memory.
A serial communication with the EM3027 starts with a
“Transmission START” and terminates with the
“Transmission STOP”.
Data in the cache memory are stable until the “Trans-
mission STOP”.
“Transmission START”
I2C
SPI
– START condition
– CS goes to ‘1’
During a write access, data are written into the cache
memory.
When the “Transmission STOP” of a WRITE trans-
mission is detected, the content of modified registers in
the cache memory is copied back into the Watch-, Alarm,
Timer- and/or Temperature-register.
“Transmission STOP”
I2C
SPI
– STOP condition
– CS goes to ‘0’
7.1
How to perform data transmission through I2C
The I2C protocol is a bidirectional protocol using 2 wires
for master-slave communication: SCL (clock) and SDA
(data). The two bus lines are driven by open drain
outputs and pulled up externally. MSB is sent first.
In the EM3027, the upper 5 bits of a register address
form a “page address”, the 3 lower bits are an auto-
incrementing sub-address. The “page-address” is defined
by a WRITE transmission. During a transmission, the 3
lower address bits are internally incremented after each
data byte.
The communication is controlled by the master. To start
a transmission, the master applies the START condition
and generates the SCL clocks during the whole
transmission. The master terminates the transmission by
sending the STOP condition.
At a READ transmission (R/W = 1), the slave sends data
and the master gives the ACK bit(s). The “page-address“
shall be defined by a WRITE transmission, completed
with the STOP condition.
The first byte contains the 7 bit slave address and the
R/W bit. The slave address must correspond to the fixed
slave address of the EM3027. After each byte, the
receiver outputs an acknowledge bit ACK to confirm
correct recept of the byte by a ‘0’ level.
The 3 lower address bits are incremented when an ACK
is received.
If ACK is not received, no auto-increment of the address
is executed and a following read outputs data of the
same address.
At a WRITE transmission (R/W = 0), the master sends
slave address, register address and data bytes.
The EM3027 works as slave. Its slave address is fixed to
‘1010110’.
I2C: Write transmission
Slave
R/W
Address
Data Byte
(1)
Data Byte
(n-1)
Data Byte
(n)
S
1010110
0
ACKs
Address
ACKs
ACKs
ACKs
ACKs
P
I2C: Read transmission
Slave
R/W
Slave
Address
R/W
Address
Data
Data
S
S
1010110
0
ACKs Address ACKs P S 1010110
1
ACKs
byte
(1)
ACKm
byte
(n)
ACKm
P
... start condition sent by the master
R/W
P
... read/write select (‘0’: master writes data)
... stop condition
ACKs ... acknowledge from the receiver (slave)
ACKm ... acknowledge from the receiver (master)
Copyright © 2009, EM Microelectronic-Marin SA
12/09 – rev D
www.emmicroelectronic.com
12
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