R
EM3027
Notes and Settings:
- Only pages 0 to 7 are used. Unused pages are for test purposes. The application should not write into unused
pages and addresses.
- The crystal offset must be set to within ± 121 ppm.
- Zero values are read from unused addresses.
- Watch, Alarm, Timer pages have to be set by an application before use.
- The bit 7 (MSB) of the Alarm registers (SecEq, MinEq.) have to be set to ‘1’ to perform the comparison. (See
paragraph 8.3)
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Definitions of terms in the memory mapping
Control Page - Register OnOffCtrl
Clk/Int
Selects if clock or interrupt is applied onto the IRQ/CLKOUT pin (’0’ = IRQ output; ’1’ = CLKOUT
output) – CLKOUT output is the default state after reset
Selects decrement rates for Timer (32 Hz after reset)
Enables Self-Recovery function (ON after reset)
TD0, TD1
SROn
EERefOn
TROn
TiOn
Enables Configuration registers refresh each 1 hour (ON after reset)
Enables Timer Auto-reload mode (‘0’ – reload disabled; ‘1’ – reload enabled)
Enables Timer (OFF after reset)
WaOn
Enables 1 Hz clock for Watch (ON after initialisation)
Control Page - Register IRQctrl
SRIntE
V2IntE
V1IntE
TIntE
Self-Recovery interrupt enable
VLOW2 interrupt enable
VLOW1 interrupt enable
Timer interrupt enable
Alarm interrupt enable
AIntE
Control Page - Register IRQflags
SRF
V2F
V1F
TF
Self-Recovery interrupt flag (bit is set to ‘1’ when Self-Recovery reset is generated)
VLOW2 interrupt flag (bit is set to ‘1’ when power drops below Vlow2)
VLOW1 interrupt flag (bit is set to ‘1’ when power drops below Vlow1)
Timer interrupt flag (bit is set to ‘1’ when Timer reaches ZERO)
Alarm interrupt flag (bit is set to ‘1’ when Watch matches Alarm)
AF
NOTE: Flags can be cleared by ‘0’ writing.
Control Page - Register Status
EEBusy
EEPROM is busy (bit is set to ‘1’ when EEPROM write or Configuration Registers refresh is in
progress) (Read Only)
PON
SR
VLOW2
VLOW1
Power ON (bit is set to ‘1’ at Power On; clear by ‘0’ writing)
Self-Recovery reset or System reset detected (clear by ‘0’ writing)
Voltage level VCC or VBack below Vlow2 level (clear by ‘0’ writing)
Voltage level VCC or VBack below Vlow1 level (clear by ‘0’ writing)
Control Page - Register RstCtrl
SYSRes System reset register; writing ‘1’ will initiate restart of the logic (Watch, Alarm and Timer parts
excluded). After the restart, status bit SR is set. The register is cleared after restart of the logic.
Watch Page - Registers Watch Seconds, Watch Minutes, Watch Hours, Watch Date, Watch Days, Watch Months,
Watch Years
Watch information (BCD format)
S12/24
PM/2
12-hours or 24-hours format selection; 12-hours: S12/24 = ‘1’, 24-hours: S12/24 = ‘0’
S12/24 = ‘0’ PM/2 represents value ‘2’ of tens,
S12/24 = ’1’ PM/2 = ‘1’ represents PM (afternoon), PM/2 =’0’ represents AM (morning)
Alarm Page - Registers Alarm Seconds, Alarm Minutes, Alarm Hours, Alarm Date, Alarm Days, Alarm Months,
Alarm Years
Alarm information (BCD format)
PM/2
S12/24 = ‘0’ PM/2 represents value ‘2’ of tens,
S12/24 = ’1’ PM/2 = ‘1’ represents PM (afternoon), PM/2 =’0’ represents AM (morning)
Copyright © 2009, EM Microelectronic-Marin SA
12/09 – rev D
www.emmicroelectronic.com
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EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
