R
A3024
bits 5 to 7 at addr. 02 hex, in accordance with Table 8. If more
than one bit is set then all the synchronization bits are disabled.
If the SYNC input is set low for longer than 200 ms, while in the
synchronization mode, the clock will synchronize to the falling
edge of the signal. Synchronization to the nearest second
implies that the 1/100 seconds are cleared to zero and if the
contents were > 50, the seconds register is incremented.
Synchronization to the nearest minute implies that the seconds
are cleared to zero and if the contents were > 30, the minutes
register is incremented. Fractions of seconds are cleared.
Alarm
An alarm date and time may be preset in RAM addresses 30 to
34 hex. The alarm function can be activated by setting the alarm
enable / disable bit (addr. 00 hex, bit 2). Once enabled the
preset alarm time and date are compared, every internal time
update cycle (10 ms), with the clock parameters in the reserved
clock area. When the clock parameters equal the alarm
parameters the alarm flag (addr. 01 hex, bit 5) is set. If the alarm
mask bit (addr. 01 hex, bit 1) is set, the IRQ pin goes active. The
alarm flag indicates to software the source of the interrupt. IRQ
will remain active until software acknowledges the interrupt by
clearing the alarm flag. If the alarm is enabled, and an alarm
address set to FF hex, this parameter is not compared with the
associated clock parameter. Thus it is possible to achieve a
repeat feature where an alarm occurs every programmed
number of seconds, or seconds and minutes, or seconds,
minutes and hours. The A3024 pulls the open drain IRQ line
active low during standby when an alarm interrupt occurs.
If the 12/24 hour mode is changed then the alarm hours
must be re-initialised.
Pulse
There are 4 programmable pulse frequencies available on the
A3024, these are every 10 ms, 100 ms, second or minute. The
pulse feature is activated by setting the pulse enable / disable
bit at address 00, bit 1. The pulse frequency is selected by
setting one of the bits 0 to 3 at address 02 hex (see Table 8). If
more than one of the pulse bits are set then the feature is
disabled. At the selected interval the pulse flag bit (addr. 01 hex,
bit 4) is set. If the pulse mask bit (addr. 01 hex, bit 0) is set then
the IRQ pin goes active. The pulse flag indicates to software the
source of the interrupt. IRQ will remain active until software
acknowledges the interrupt by clearing the pulse flag. The
pulse feature is disabled while in standby. Upon power
restoration the pulse feature is enabled if enabled prior to
standby. See also the section "Frequency Tuning".
Note: The user should ensure that a time lapse of at least 60
microseconds exists between the falling edge of the IRQ and
the clearing of the alarm flag.
IRQ
The IRQ output is used by 4 of the A3024's features.
These are:
1) Pulse, to provide periodic interrupts to the microprocessor
at preprogrammed intervals;
Note: The user should ensure that a time lapse of at least 60
microseconds exists between the falling edge of the IRQ and
the clearing of the pulse flag.
2) Alarm to provide an interrupt to the microprocessor at a
preprogrammed time and date;
Time Set Lock
3) Timer, to provide an interrupt to the microprocessor when
the timer rolls over from 23:59:59:99 to 00:00:00:00; and
The time set lock control bit is located at address 00 hex, bit 5
(see Table 6). When set by software, this bit disables any
transfer from the RAM to the reserved clock and timer area as
well as inhibiting any write to the digital trimming register at
address 10 hex. When the time set lock bit is set the following
transfer operations are disabled:
4) Frequency trimming (see section "Frequency Trimming").
The first 3 features listed are similar in the way they provide
interrupts to the microprocessor. Each of the 3 has an enable /
disable bit, a flag bit, and an interrupt mask bit. The enable /
disable bit allows software to select a feature or not. A set flag bit
indicates that an enable feature has reached its interrupt
condition. Software must clear the flag bit. The interrupt mask
bit allows or disallows the IRQ output to become active when
the flag bit is set. The IRQ output becomes active whenever any
interrupt flag is set which also has its mask bit set. For all
sources of maskable interrupts within the A3024, the IRQ output
will remain active until software clears the interrupt flag. The IRQ
output is the logical OR of all the unmasked interrupt flags. The
IRQ output is open drain so an external pullup to VDD is needed.
In standby (PF active) the IRQ output will be active if the alarm
mask bit (addr. 01 hex, bit 1) is set and the alarm flag is also set.
The timer or the pulse feature cannot cause the IRQ output to
become active while in standby.
The clock command followed by write,
the timer command followed by write,
the clock and timer command followed by write, and
writing to the digital trimming register.
A set bit prevents unauthorized overwriting of the reserved
clock and timer area. Reading of the reserved clock and timer
area, using the commands, is not affected by the time set lock
bit. Clearing the time set lock bit by software will re-enable the
above listed commands. On initialisation the time set lock bit is
cleared. The time set lock bit does not affect the user RAM (addr.
50 to 5F hex).
Frequency Tuning
The A3024 offers a key feature called "Digital Trimming", which
is used for the clock accuracy adjustment. Unlike the traditional
capacitor trimming method, which tunes the crystal oscillator,
the digital trimming acts on the divider chain, allowing the clock
adjustment by software. The oscillator frequency itself is not
affected.
Synchronization
There are 3 ways to synchronize the A3024. It can be
synchronized to 50 Hz, the nearest second, or the nearest
minute. Synchronization mode is selected by setting one of the
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EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
