R
A3024
reserved clock and timer area.
Communication
The commands take place in two steps as do all other
communications. The command address is sent with A/D low.
This is followed by either a read (RD) or a write (WR), with A/D
high, to determine the direction of the transfer. If the second
step is a read then the data is transferred from the reserved
clock and timer area to the RAM and if the second step is a write
then the data that has already been loaded into the RAM clock
and/or timer locations is transferred to the reserved clock
and/or timer area.
Data transfer is in 8 bit parallel form. All time data is in packed
BCD format with tens data on lines AD 7 - 4 and units on lines
AD 3 - 0. To access information within the RAM (see Fig. 7) first
write the RAM address, then read or write from or to this
location. Fig 8 shows the two steps needed.
The lines AD 0 - 7 will be treated as an address when pin A/D is
low, and as data when A/D is high. Pin A/D must not change
state during any single read or write access. One line of the
address bus (e.g. A0) can be used to implement the A/D signal
(see "Typical Operating Configuration", Fig. 1). Until a new
address is written, data accesses (A/D high) will always be to
the same RAM address.
Clock and Calendar
The time and date locations in RAM (see Table 9) provide
access to the 1/100 seconds, seconds, minutes, hours, date,
month, year, week day, and week number. These parameters
have the ranges indicated in Table 9. The A3024 may be
programmed for 12 or 24 hour time format (see section "12/24
Data Format"). If a parameter is found to be out of range, it will
be cleared when the units value on its being next incremented is
equal to or greater than 9 eg. B2 will be set to 00 after the units
have incremented to 9 (ie. B9 to 00). The device incorporates
leap year correction and week number calculation at the
beginning of a year. If the first day of the year is day 05, 06 or 07
of the week, then it is given a zero week number, otherwise it
becomes week one. Week days are numbered from 1 to 7 with
Monday as day 1.
Communication Sequence
Write RAM address
to the A3024
A/D = 0
Read or write data from or to
A/D = 1
the above address
Fig. 8
Access Considerations
The communication sequence shown in Fig. 8 is re-entrant.
When the address is written to the A3024 (ie. first step of the
communication sequence) it is stored in an internal address
latch. Software can read the internal address latch at any time
by holding the A/D line low during a read from the A3024. So, for
example, an interrupt routine can read the address latch and
push it onto a stack, popping it when finished to restore the
A3024.
Reading of the current time and date must be preceded by a
clock command. The time and date from the last clock
command is held unchanged in RAM.
When transferring data to the reserved clock and timer area
remember to clear the time set lock bit first.
Timer
The timer can be used either for counting elapsed time, or for
giving an interrupt (IRQ) on being incremented from
23:59:59:99 to 00:00:00:00. The timer counts up with a
resolution of 1/100 second in the timer reserved areas. The
timer enable / disable bit (addr. 00 hex, bit 3) must be set by
software to allow the timer to be incremented. The timer is
incremented in the reserved timer area, every internal time
update (10 ms). The timer flag (addr. 01 hex, bit 6) is set when
the timer rolls over from 23:59:59:99 to 00:00:00:00 and the IRQ
becomes active if the timer mask bit (addr. 01, bit 2) is set. The
IRQ will remain active until software acknowledges the interrupt
by clearing the timer flag. The timer is incremented in the
standby mode, however it will not cause IRQ to become active
until power (VDD) has been restored.
NB. Alarm and timer interrupt routines can reprogram the alarm
and timer without it being necessary to read or reprogram the
clock.
Commands
The commands allow software to transfer the clock and timer
parameters in a sequence (eg. seconds, minutes, hours, etc.)
without any danger of an internal time update with carry over
corrupting the data. They also avoid delaying internal time
updates while using the A3024, as updates occuring in the
reserved clock and timer area are invisible to software. Software
writes or reads parameters to or from the RAM only.
There are three commands that occupy the command address
space in the RAM. The function of these commands is to
transfer data from the reserved clock and timer area to the RAM
or to transfer data in the opposite direction, from the RAM to the
Note: The user should ensure that a time lapse of at least 60
microseconds exists between the falling edge of the IRQ and
the clearing of the timer flag.
10
EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
