R
A3024
initialisation bit (addr. 2 bit 4) and then a 0. This sets the
Pin Description
DIP20 and SO20 Packages
Frequency Tuning bit and clears all other status bits.
The time and date parameters should then be loaded into the
RAM (addr. 20 to 28 hex) and then transferred to the reserved
clock area using the clock command followed by a write.
Pin Name Description
1
2
SYNC Time synchronization
I
PF
I
Power fail
The digital trimming register must then be initialised by
writing 210 (D2 hex) to it, if Frequency Tuning is not
required. After having written a value to the digital
trimming register the frequency tuning mode bit can be
cleared.
AD0
AD1
AD2
AD3
A/D
IRQ
VSS
3
Bit 0 from MUX address / data bus
Bit 1 from MUX address / data bus
Bit 2 from MUX address / data bus
Bit 3 from MUX address / data bus
Address / data decode
I/O
I/O
I/O
I/O
I
4
5
6
7
RAM Configuration
8
Interrupt request
O
The RAM area of the A 3024 has a reserved clock and time area,
a data space, user RAM and an address command space (see
Table 9 or Fig. 7). The reserved clock and timer area is not
directly accessible to the user, it is used for internal time
keeping and contains the current time and date plus the timer
parameters.
9
Supply ground (substrate)
Oscillator input
GND
I
XIN
10
11 XOUT
Oscillator output
O
Positive supply terminal
Chip select
PWR
I
12
13
14
15
16
17
18
19
20
VDD
CS
WR (Intel) or R/W (Motorola)
RD (Intel) or DS (Motorola)
Bit 4 from MUX address / data bus
Bit 5 from MUX address / data bus
Bit 6 from MUX address / data bus
Bit 7 from MUX address / data bus
No connection
I
WR
RD
Data Space
All locations in the data space are Read/Write. The data space
is directly accessible to the user and is divided into five areas :
I
I/O
I/O
I/O
I/O
-
AD4
AD5
AD6
AD7
NC
Status Registers - three registers used for status and control
data for the device (see Tables 6, 7 and 8).
Digital Trimming Register - a special function described
under “Frequency Tuning”.
Table 5
Time and Date Registers - 9 time and date locations which are
loaded with, either the current time and date parameters from
the reserved clock area or the time and date parameters to be
transferred to the reserved clock area.
Functional Description
Power Supply, Data Retention and Standby
The A3024 is put in standby mode by activating the PF input.
When pulled logic low, PF will disable the input lines, and
immediately take to high impedance the lines AD 0-7. Input
states must be under control whenever PF is deactivated. If no
specific power fail signal can be provided, PF can be tied to the
system RESET. Even in standby the interrupt request pin IRQ
will pull to ground upon an unmasked alarm interrupt
occurring.
Alarm Registers - 5 locations used for setting the alarm
parameters.
Timer Registers - 4 locations which are loaded with either the
timer parameters from the reserved timer area or the timer
parameters to be transferred to the reserved time area.
User RAM
The A3024 has 16 bytes of general purpose RAM available for
the users applications. This RAM block is located at addresses
50 to 5F hex and is maintained even in the standby mode (PF
active). The commands, or the time set lock bit, have no effect
on the user RAM block. Reading or writing to the user RAM is
similar to reading or writing to any system RAM address.
Initialisation
When power is first applied to the A3024 all registers have a
random value.
To initialise the A3024, software must first write a 1 to the
8
EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
