R
A3024
General Block Diagram
X
in
X
out
100 Hz
Oscillator and
Divider Chain
8
Trim Bus
Trimming and Alarm
Logic
Clock
and
Timer
00
01
02
10
20
status 0
status 1
status 2
digital trimming
clock
alarm
timer
16 bytes of user RAM
5F
F0 clock and timer command
F1 clock command
F2 timer command
43
50
Reserved clock
and timer area
Hex Address
28
30
34
40
RAM
(data space)
Address / Data
A/D
CS
WR
RD
SYNC
Control Block and
Output Buffers
RAM
(address command space)
Address / Data
Control Bus
IRQ + PF
Logic
IRQ
Power Fail
Digital Trimming
IRQ
32768 Hz
1kHz
Oscillator
INIB.
Reg.
INIB.RAM
:42/43
:32
:10
100 Hz
Timer
1/100 Sec. Min. Hour
:31
Timer RAM
Reset WR F0 F1
INIT. Bit
Reset INIT
Alarm RAM
COMP
Reset WR F2
Reset WR F1
8
Reset Logic
Write F0, F1, F2
Clock RAM
:10
100 Hz
1 Hz
Clock
1/100 Sec. Min. Hour Day Month Year W/D W #
Fig. 7
7
EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
