ePVP6800
VFD Controller
13 Key & Switch Scanning and Display Timing
The key & switch scanning and display timing diagram is given below. One cycle of key & switch
scanning consists of 2 frames. The data of the 4 x 4 matrix is stored in the RAM.
31.25us
470us
500us
16/16
GRID 1
output
1/16
4/16
6/16
8/16
10/16
12/16
14/16
GRID 2
output
SEG 1
output
SEG 2
output
SEG 3
output
DISP≒500us
Key& Switchscandata
DIG1
GRID 1
GRID 2 GRID 3
GRID
n
GRID 1
output
GRID 2
output
GRID 3
output
GRID n
output
4/16
1/16
10/16
2/16
SEG1
output
14/16
SEG2
2/16
output
SEG3
output
SEGn
output
1frame=TDISP*(n+1)
Fig. 15 Key & Switch Scanning and Display Timing Diagram
40 of 47 11. 28.2004 (V1.23)
This specification is subject to change without further notice.
ELAN [ ELAN MICROELECTRONICS CORP ]
