EM78P510N
8-Bit Microcontrollers
Bit 4 (SPIE): Interrupt Enable Bit
0 : disable SPIF interrupt
1 : enable SPIF interrupt
Related Status/Data Registers of the SPI Mode
Address
0X0C
Name
SPIS
SPIR
SPIW
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DORD
TD1
TD0
-
OD3
OD4
-
RBF
0x0E
SRB7 SRB6 SRB5 SRB4 SRB3 SRB2 SRB1 SRB0
SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0
0x0F
SPIS: SPI Status Register
Bit 7 (DORD): Data Shift Control Bit
0 : Shift left (MSB first)
1 : Shift right (LSB first).
Bits 6~5 (TD1~TD0): SDO Status Output Delay Times Options
TD1
0
TD0
0
Delay Time
8 CLK
0
1
16 CLK
24 CLK
32 CLK
1
0
1
1
Bit 4: Reserved
Bit 3 (OD3): Open-Drain Control Bit
1 : Open-drain enable for SDO
0 : Open-drain disable for SDO.
Bit 2 (OD4): Open-Drain Control Bit
1 : Open-drain enable for SCK
0 : Open-drain disable for SCK.
Bit 1:
Reserved
Bit 0 (RBF): Read Buffer Full Flag
1 : Receiving completed, and SPIRB is fully exchanged.
0 : Receiving not completed, and SPIRB has not fully exchanged.
SPIRB:
SPIWB:
SPI Read Buffer. Once the serial data is received completely, it will load to
SPIRB from SPIS register. The RBF bit in the SPIS register will also be set.
SPI Write Buffer. As a transmitted data is loaded, the SPIS register
stands by and start to shift the data when sensing SCK edge with SSE set
to “1”.
Product Specification (V0.9) 09.12.2006
(This specification is subject to change without further notice)
• 83
ELAN [ ELAN MICROELECTRONICS CORP ]
