EM78P510N
8-Bit Microcontrollers
Bit 7 (CES): Clock Edge Select Bit
0 : Data shifts out on a rising edge, and shifts in on a falling edge. Data is
on hold during a low-level.
1 : Data shifts out on a falling edge, and shifts in on a rising edge. Data is
on hold during a high-level.
Bit 6 (SPIE): SPI Enable Bit
0 : Disable SPI mode
1 : Enable SPI mode
Bit 5 (SRO): SPI Read Overflow Bit
0 : No overflow
1 : A new data is received while the previous data is still being held in the
SPIRB register. In the situation, the data in SPIS register will be
destroyed. To avoid setting this bit, users are required to read the
SPIRB register although only the transmission is implemented. This
can only occur in slave mode.
Bit 4 (SSE): SPI Shift Enable Bit
0 : Resets as soon as the shift is completed, and the next byte is read to
shift.
1 : Starts to shift, and remained on “1” while the current byte is still being
transmitted.
Bit 3 (SDOC): SDO Output Status Control Bit
0 : After the serial data output, the SDO remain high.
1 : After the serial data output, the SDO remain low.
Bits 2~0 (SBRS2~SBRS0): SPI Baud Rate Select Bits
SBRS2
SBRS1
SBRS0
Mode
Master
Master
Master
Master
Master
Master
Slave
SPI Baud Rate
Fosc/2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Fosc/4
Fosc/8
Fosc/16
Fosc/32
Timer2
/SS enable
/SS disable
Slave
IMR:
Interrupt Mask Register
82 •
Product Specification (V0.9) 09.12.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
