EM78P458/459
OTP ROM
1 = The Vref of the ADC is connected to P53/VREF.
• CE (Bit 6): Control bit used to enable comparator.
0 = Disable comparator
1 = Enable comparator
• COE (Bit 5): Set P57 as the output of the comparator
0 = the comparator acts as an OP if CE=1.
1 = act as a comparator if CE=1.
• IMS2~IMS0 (Bit 4 ~ Bit 2): ADC configuration definition bit.
• CKR1 and CKR0 (Bit 1 and Bit 0): The conversion time select.
00 = Fosc/4;
01 = Fosc/16;
10 = Fsco/64;
11 = The oscillator clock source of ADC is from WDT ring oscillator frequency.
( frequency=256/18ms≒14.2Khz)
1.3 GCON/IOC90
As shown in Fig. 12, OP1 and OP2, the gain amplifiers, are located in the middle of the analog
input pins (ADC1 and ADC5) and the 8-1analog switch. The GCON register controls the gains.
Table 7 Table 7 Shows the Gains and the Operating Range of ADC.
BIT
SYMBOL
*Init_Value
7
OP2E
0
6
OP1E
0
5
G22
0
4
G21
0
3
G20
0
2
G12
0
1
G11
0
0
G10
0
Table 8 The Gains and the Operating Range of ADC
G10:G12/G20:G22
Gain
1
Range of Operating Voltage
0 ~ Vref
000
001
010
011
100
101
2
0 ~ (1/2)Vref
4
8
16
32
0 ~ (1/4)Vref
0 ~ (1/8)Vref
0 ~ (1/16)Vref
0 ~ (1/32)Vref
<Note> Vref can not be less than 3 volts.
2. ADC Data Register (ADDATA/RA)
When the A/D conversion is complete, the result is loaded to the ADDATA. The START/END bit is
clear, and the ADIF is set.
This specification is subject to change without prior notice.
33
06.25.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
