EM78P447S
OTP ROM
6. ELECTRICAL CHARACTERISTICS
6.1 DC Electrical Characteristic
( Ta= 0°C ~ 70 °C, VDD= 5.0V±5%, VSS= 0V )
Symbol
Parameter
Condition
Two cycle with two clocks
Two cycle with two clocks
R: 5.1KΩ, C: 100 pF
VIN = VDD, VSS
Ports 5, 6
Min
DC
Typ.
950
Max
8.0
Unit
MHz
MHz
KHz
µA
XTAL: VDD to 3V
XTAL: VDD to 5V
ERC: VDD to 5V
FXT
DC
20.0
F±30%
±1
ERC
IIL
VIH1
VIL1
F±30%
Input Leakage Current for input pins
Input High Voltage (VDD=5V)
Input Low Voltage (VDD=5V)
Input High Threshold Voltage
(VDD=5V)
2.0
2.0
V
Ports 5, 6
0.8
V
VIHT1
/RESET, TCC
V
Input Low Threshold Voltage
(VDD=5V)
VIHX1 Clock Input High Voltage (VDD=5V)
VILX1 Clock Input Low Voltage (VDD=5V)
VILT1
/RESET, TCC
0.8
V
OSCI
OSCI
Ports 5, 6
Ports 5, 6
3.5
1.5
V
V
V
V
1.5
0.4
VIH2
VIL2
Input High Voltage (VDD=3V)
Input Low Voltage (VDD=3V)
Input High Threshold Voltage
(VDD=3V)
VIHT2
/RESET, TCC
1.5
V
Input Low Threshold Voltage
(VDD=3V)
VILT2
/RESET, TCC
0.4
0.9
V
VIHX2 Clock Input High Voltage (VDD=3V)
VILX2 Clock Input Low Voltage (VDD=3V)
OSCI
OSCI
2.1
2.4
V
V
Output High Voltage
VOH1
IOH = -10.0 mA
IOL = 9.0 mA
IOL = 14.0 mA
V
(Ports 5, 6, 7)
Output Low Voltage
VOL1
0.4
V
(Ports 5, 6)
Output Low Voltage
VOL2
0.4
-240
1
V
(Port7)
IPH
Pull-high current
Pull-high active, input pin at VSS
All input and I/O pins at VDD,
output pin floating, WDT disabled
All input and I/O pins at VDD,
output pin floating, WDT enabled
/RESET= 'High', Fosc=32KHz
(Crystal type,CLKS="0"), output
pin floating, WDT disabled
/RESET= 'High', Fosc=32KHz
(Crystal type,CLKS="0"), output
pin floating, WDT enabled
/RESET= 'High', Fosc=4MHz
(Crystal type, CLKS="0"), output
pin floating, WDT enabled
-50
15
-100
µA
µA
ISB1
Power down current
ISB2
ICC1
Power down current
7
µA
µA
Operating supply current
(VDD=3V)
25
30
30
at two cycles/four clocks
Operating supply current
(VDD=3V)
ICC2
ICC3
ICC4
35
2.2
5.0
µA
mA
mA
at two cycles/four clocks
Operating supply current
(VDD=5V)
at two cycles/two clocks
Operating supply current
(VDD=5V)
/RESET= 'High', Fosc=10MHz
(Crystal type, CLKS="0"), output
pin floating, WDT enabled
at two cycles/four clocks
This specification is subject to change without prior notice.
35
06.25.2003 (V1.1)