EM78P447S
OTP ROM
6. IOCF (Interrupt Mask Register)
7
6
-
5
-
4
-
3
2
-
1
-
0
-
EXIE
TCIE
• Bit 3 (EXIE) EXIF interrupt enable bit.
0: disable EXIF interrupt
1: enable EXIF interrupt
• Bit 0 (TCIE) TCIF interrupt enable bit.
0: disable TCIF interrupt
1: enable TCIF interrupt
• Bits 1, 2 and 4~7 Not used.
• Individual interrupt is enabled by setting its associated control bit in the IOCF to "1".
• Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction (refer to Fig.
9).
• IOCF register is both readable and writable.
/WUE0
Oscillator
Enable
Disable
/WUE1
/WUE7
Reset
PR
Q
Q
D
CLK
VCC
CL
Clear
from S/W
Set
8
P60~P67
VCC
/WUE
2
/PHEN
P74~P75
Fig. 5 Sleep Mode and Wake-Up Circuits on I/O Ports Block Diagram
This specification is subject to change without prior notice.
15
06.25.2003 (V1.1)
ELAN [ ELAN MICROELECTRONICS CORP ]
